Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	71893584	146517	0	0
StatusRise_A	71893584	163423	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71893584	146517	0	0
T1	29934	201	0	0
T2	5730	15	0	0
T3	41049	33	0	0
T4	310194	391	0	0
T5	45405	3	0	0
T6	12207	27	0	0
T7	48276	49	0	0
T8	6162	3	0	0
T9	9105	24	0	0
T10	55059	93	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71893584	163423	0	0
T1	29934	206	0	0
T2	5730	18	0	0
T3	41049	36	0	0
T4	310194	437	0	0
T5	45405	6	0	0
T6	12207	30	0	0
T7	48276	51	0	0
T8	6162	6	0	0
T9	9105	27	0	0
T10	55059	96	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23964528	54351	0	0
StatusRise_A	23964528	60481	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23964528	54351	0	0
T1	9978	79	0	0
T2	1910	5	0	0
T3	13683	14	0	0
T4	103398	144	0	0
T5	15135	1	0	0
T6	4069	9	0	0
T7	16092	19	0	0
T8	2054	1	0	0
T9	3035	8	0	0
T10	18353	35	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23964528	60481	0	0
T1	9978	81	0	0
T2	1910	6	0	0
T3	13683	15	0	0
T4	103398	160	0	0
T5	15135	2	0	0
T6	4069	10	0	0
T7	16092	20	0	0
T8	2054	2	0	0
T9	3035	9	0	0
T10	18353	36	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23964528	54351	0	0
StatusRise_A	23964528	60481	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23964528	54351	0	0
T1	9978	79	0	0
T2	1910	5	0	0
T3	13683	14	0	0
T4	103398	144	0	0
T5	15135	1	0	0
T6	4069	9	0	0
T7	16092	19	0	0
T8	2054	1	0	0
T9	3035	8	0	0
T10	18353	35	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23964528	60481	0	0
T1	9978	81	0	0
T2	1910	6	0	0
T3	13683	15	0	0
T4	103398	160	0	0
T5	15135	2	0	0
T6	4069	10	0	0
T7	16092	20	0	0
T8	2054	2	0	0
T9	3035	9	0	0
T10	18353	36	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23964528	37815	0	0
StatusRise_A	23964528	42461	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23964528	37815	0	0
T1	9978	43	0	0
T2	1910	5	0	0
T3	13683	5	0	0
T4	103398	103	0	0
T5	15135	1	0	0
T6	4069	9	0	0
T7	16092	11	0	0
T8	2054	1	0	0
T9	3035	8	0	0
T10	18353	23	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23964528	42461	0	0
T1	9978	44	0	0
T2	1910	6	0	0
T3	13683	6	0	0
T4	103398	117	0	0
T5	15135	2	0	0
T6	4069	10	0	0
T7	16092	11	0	0
T8	2054	2	0	0
T9	3035	9	0	0
T10	18353	24	0	0