Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	23965133	5859	0	0
EscTimeoutStoppedByClReset_A	23964528	3271043	0	0
EscTimeoutTriggersReset_A	5128357	332	0	0
RomAllowActiveState_A	23964528	60114	0	0
RomAllowCheckGoodState_A	23964528	60164	0	0
RomBlockActiveState_A	23964528	24942	0	0
RomBlockCheckGoodState_A	23964528	405191	0	0
RomIntgChkDisFalse_A	23964528	23279989	0	0
RomIntgChkDisTrue_A	23964528	160762	0	0
RstreqChkEsctimeout_A	23964528	4456	0	0
RstreqChkFsmterm_A	23964528	140	0	0
RstreqChkGlbesc_A	23964528	4456	0	0
RstreqChkMainpd_A	23964528	933380	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23965133	5859	0	0
T5	15136	59	0	0
T6	4070	0	0	0
T7	16093	0	0	0
T8	2054	0	0	0
T9	3035	0	0	0
T10	18354	0	0	0
T11	516	0	0	0
T12	0	19	0	0
T13	1362	0	0	0
T14	1108	0	0	0
T18	13029	0	0	0
T36	0	173	0	0
T37	0	26	0	0
T145	0	71	0	0
T146	0	2	0	0
T147	0	7	0	0
T148	0	54	0	0
T149	0	5	0	0
T150	0	145	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23964528	3271043	0	0
T1	9978	1662	0	0
T2	1910	113	0	0
T3	13683	2734	0	0
T4	103398	16249	0	0
T5	15135	9	0	0
T6	4069	321	0	0
T7	16092	4469	0	0
T8	2054	0	0	0
T9	3035	403	0	0
T10	18353	3778	0	0
T18	0	2274	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5128357	332	0	0
T5	742	3	0	0
T6	1405	0	0	0
T7	1790	0	0	0
T8	190	0	0	0
T9	304	0	0	0
T10	2002	0	0	0
T11	557	10	0	0
T12	0	4	0	0
T13	575	0	0	0
T14	338	0	0	0
T18	2610	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T137	0	3	0	0
T145	0	3	0	0
T146	0	4	0	0
T147	0	5	0	0
T151	0	4	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23964528	60114	0	0
T1	9978	81	0	0
T2	1910	6	0	0
T3	13683	15	0	0
T4	103398	160	0	0
T5	15135	2	0	0
T6	4069	10	0	0
T7	16092	20	0	0
T8	2054	2	0	0
T9	3035	9	0	0
T10	18353	36	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23964528	60164	0	0
T1	9978	81	0	0
T2	1910	6	0	0
T3	13683	15	0	0
T4	103398	160	0	0
T5	15135	2	0	0
T6	4069	10	0	0
T7	16092	20	0	0
T8	2054	2	0	0
T9	3035	9	0	0
T10	18353	36	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23964528	24942	0	0
T2	1910	309	0	0
T3	13683	0	0	0
T4	103398	0	0	0
T5	15135	0	0	0
T6	4069	0	0	0
T7	16092	0	0	0
T8	2054	0	0	0
T9	3035	0	0	0
T10	18353	0	0	0
T18	13029	0	0	0
T25	0	898	0	0
T32	0	3	0	0
T33	0	8	0	0
T35	0	611	0	0
T38	0	1026	0	0
T136	0	27	0	0
T152	0	5	0	0
T153	0	76	0	0
T154	0	207	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23964528	405191	0	0
T1	9978	687	0	0
T2	1910	95	0	0
T3	13683	0	0	0
T4	103398	574	0	0
T5	15135	0	0	0
T6	4069	0	0	0
T7	16092	0	0	0
T8	2054	0	0	0
T9	3035	0	0	0
T10	18353	459	0	0
T25	0	1048	0	0
T26	0	4148	0	0
T32	0	928	0	0
T33	0	1307	0	0
T34	0	593	0	0
T35	0	219	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23964528	23279989	0	0
T1	9978	9835	0	0
T2	1910	873	0	0
T3	13683	13584	0	0
T4	103398	102240	0	0
T5	15135	15056	0	0
T6	4069	3987	0	0
T7	16092	16032	0	0
T8	2054	1993	0	0
T9	3035	2984	0	0
T10	18353	18275	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23964528	160762	0	0
T2	1910	950	0	0
T3	13683	0	0	0
T4	103398	0	0	0
T5	15135	0	0	0
T6	4069	0	0	0
T7	16092	0	0	0
T8	2054	0	0	0
T9	3035	0	0	0
T10	18353	0	0	0
T18	13029	0	0	0
T25	0	1445	0	0
T26	0	1696	0	0
T35	0	109	0	0
T38	0	2851	0	0
T152	0	285	0	0
T153	0	759	0	0
T155	0	2203	0	0
T156	0	1018	0	0
T157	0	1918	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23964528	4456	0	0
T2	1910	3	0	0
T3	13683	0	0	0
T4	103398	5	0	0
T5	15135	1	0	0
T6	4069	0	0	0
T7	16092	0	0	0
T8	2054	0	0	0
T9	3035	3	0	0
T10	18353	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T18	13029	10	0	0
T25	0	3	0	0
T36	0	1	0	0
T37	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23964528	140	0	0
T11	516	0	0	0
T12	1379	0	0	0
T13	1361	0	0	0
T14	1107	0	0	0
T18	13029	20	0	0
T19	0	40	0	0
T20	0	20	0	0
T25	4922	0	0	0
T26	60543	0	0	0
T27	0	20	0	0
T28	0	40	0	0
T29	5082	0	0	0
T30	1070	0	0	0
T31	2588	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23964528	4456	0	0
T2	1910	3	0	0
T3	13683	0	0	0
T4	103398	5	0	0
T5	15135	1	0	0
T6	4069	0	0	0
T7	16092	0	0	0
T8	2054	0	0	0
T9	3035	3	0	0
T10	18353	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T18	13029	10	0	0
T25	0	3	0	0
T36	0	1	0	0
T37	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23964528	933380	0	0
T1	9978	645	0	0
T2	1910	50	0	0
T3	13683	0	0	0
T4	103398	2606	0	0
T5	15135	0	0	0
T6	4069	0	0	0
T7	16092	0	0	0
T8	2054	0	0	0
T9	3035	366	0	0
T10	18353	2605	0	0
T15	0	11	0	0
T26	0	5298	0	0
T32	0	1186	0	0
T33	0	1156	0	0
T34	0	1206	0	0