Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	521328	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

195962

1

T1

26

T2

89

T3

50

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	371813	1			T1	182		T2	194		T3	90
values[0x0]	172295	1			T1	31		T2	91		T3	17
values[0x1]	173182	1			T1	31		T2	91		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	412791	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

304499

1

T1

96

T2

151

T3

64

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2260	1			T2	4		T3	5		T4	11
valid_sources[0x01]	2512	1			T1	9		T5	1		T25	2
valid_sources[0x02]	2234	1			T2	1		T7	1		T25	1
valid_sources[0x03]	5013	1			T5	1		T7	6		T25	2
valid_sources[0x04]	2164	1			T2	4		T7	1		T25	1
valid_sources[0x05]	2515	1			T1	10		T2	1		T4	12
valid_sources[0x06]	2167	1			T4	11		T7	3		T25	2
valid_sources[0x07]	2612	1			T4	12		T7	2		T22	6
valid_sources[0x08]	2331	1			T7	2		T25	1		T22	17
valid_sources[0x09]	2506	1			T41	1		T25	1		T56	2
valid_sources[0x0a]	2541	1			T7	7		T25	2		T22	5
valid_sources[0x0b]	2496	1			T2	4		T38	2		T22	3
valid_sources[0x0c]	2411	1			T2	3		T7	1		T22	4
valid_sources[0x0d]	2491	1			T1	8		T2	1		T38	2
valid_sources[0x0e]	2275	1			T4	11		T56	1		T22	3
valid_sources[0x0f]	3348	1			T2	1		T3	2		T4	11
valid_sources[0x10]	2345	1			T2	2		T25	1		T56	1
valid_sources[0x11]	4468	1			T4	11		T22	4		T20	17
valid_sources[0x12]	3114	1			T2	12		T25	4		T22	2
valid_sources[0x13]	3123	1			T1	7		T2	1		T5	1
valid_sources[0x14]	2638	1			T2	3		T7	3		T56	1
valid_sources[0x15]	3239	1			T2	1		T7	1		T38	2
valid_sources[0x16]	2635	1			T4	11		T7	1		T25	3
valid_sources[0x17]	3112	1			T1	2		T3	4		T4	11
valid_sources[0x18]	2268	1			T1	9		T4	11		T25	1
valid_sources[0x19]	2250	1			T1	1		T4	33		T22	1
valid_sources[0x1a]	2433	1			T2	1		T7	3		T56	1
valid_sources[0x1b]	2410	1			T1	2		T25	3		T56	1
valid_sources[0x1c]	2243	1			T4	11		T25	2		T56	1
valid_sources[0x1d]	3236	1			T1	7		T2	2		T22	10
valid_sources[0x1e]	3373	1			T4	11		T7	1		T25	1
valid_sources[0x1f]	2259	1			T2	4		T4	11		T25	3
valid_sources[0x20]	2308	1			T56	2		T22	5		T20	9
valid_sources[0x21]	2087	1			T2	1		T56	3		T11	1
valid_sources[0x22]	2578	1			T4	23		T7	1		T25	1
valid_sources[0x23]	3455	1			T1	4		T4	12		T7	3
valid_sources[0x24]	4491	1			T2	4		T4	1682		T7	6
valid_sources[0x25]	2398	1			T2	1		T4	11		T25	4
valid_sources[0x26]	2595	1			T5	1		T20	21		T24	3
valid_sources[0x27]	2249	1			T5	1		T25	5		T20	15
valid_sources[0x28]	2367	1			T4	11		T25	1		T20	18
valid_sources[0x29]	2426	1			T4	22		T25	1		T56	1
valid_sources[0x2a]	2267	1			T2	5		T4	11		T7	3
valid_sources[0x2b]	2695	1			T2	2		T4	521		T13	6
valid_sources[0x2c]	3468	1			T7	2		T25	2		T56	1
valid_sources[0x2d]	3522	1			T1	1		T4	867		T5	1
valid_sources[0x2e]	2354	1			T20	18		T59	1		T21	26
valid_sources[0x2f]	2368	1			T5	1		T56	2		T20	15
valid_sources[0x30]	2468	1			T2	4		T3	14		T38	2
valid_sources[0x31]	5106	1			T2	4		T25	2		T56	1
valid_sources[0x32]	2505	1			T4	11		T6	8		T7	3
valid_sources[0x33]	4113	1			T2	1		T3	2		T38	1
valid_sources[0x34]	2651	1			T4	417		T22	3		T20	14
valid_sources[0x35]	2607	1			T56	1		T22	1		T20	12
valid_sources[0x36]	2216	1			T7	21		T56	1		T22	11
valid_sources[0x37]	2150	1			T38	4		T25	1		T56	1
valid_sources[0x38]	2253	1			T22	5		T20	31		T59	1
valid_sources[0x39]	2811	1			T2	14		T4	23		T25	3
valid_sources[0x3a]	2600	1			T2	12		T5	2		T7	3
valid_sources[0x3b]	2266	1			T56	1		T22	2		T20	27
valid_sources[0x3c]	2552	1			T1	12		T4	11		T20	27
valid_sources[0x3d]	2686	1			T1	1		T2	2		T4	11
valid_sources[0x3e]	2463	1			T1	8		T2	4		T4	11
valid_sources[0x3f]	2665	1			T2	3		T25	1		T20	15
valid_sources[0x40]	3807	1			T2	3		T4	22		T7	3
valid_sources[0x41]	2237	1			T7	1		T25	1		T56	2
valid_sources[0x42]	2929	1			T1	8		T56	1		T20	13
valid_sources[0x43]	2889	1			T3	2		T4	11		T25	1
valid_sources[0x44]	2163	1			T1	3		T4	11		T7	1
valid_sources[0x45]	2564	1			T2	3		T25	1		T22	1
valid_sources[0x46]	2578	1			T2	7		T4	22		T7	1
valid_sources[0x47]	2470	1			T1	7		T25	4		T56	1
valid_sources[0x48]	2658	1			T4	24		T25	1		T56	3
valid_sources[0x49]	2598	1			T1	2		T2	4		T4	11
valid_sources[0x4a]	3350	1			T1	6		T4	884		T7	5
valid_sources[0x4b]	2359	1			T1	2		T2	1		T5	1
valid_sources[0x4c]	3642	1			T2	1		T25	1		T20	19
valid_sources[0x4d]	4226	1			T2	1		T4	12		T7	3
valid_sources[0x4e]	2262	1			T1	4		T38	4		T25	1
valid_sources[0x4f]	2744	1			T1	3		T2	1		T25	2
valid_sources[0x50]	3786	1			T4	1038		T25	9		T22	6
valid_sources[0x51]	3379	1			T4	43		T7	2		T22	4
valid_sources[0x52]	2500	1			T1	3		T3	1		T7	3
valid_sources[0x53]	2434	1			T2	2		T4	12		T6	12
valid_sources[0x54]	2355	1			T3	8		T4	11		T5	1
valid_sources[0x55]	2436	1			T4	11		T25	1		T22	7
valid_sources[0x56]	2367	1			T2	5		T7	3		T56	1
valid_sources[0x57]	3357	1			T3	1		T22	11		T20	14
valid_sources[0x58]	4005	1			T2	3		T4	1783		T56	2
valid_sources[0x59]	2434	1			T4	23		T5	3		T7	1
valid_sources[0x5a]	2604	1			T25	2		T56	2		T22	3
valid_sources[0x5b]	2448	1			T7	2		T25	1		T22	5
valid_sources[0x5c]	2589	1			T3	4		T4	11		T8	1
valid_sources[0x5d]	2621	1			T3	5		T4	11		T25	1
valid_sources[0x5e]	2457	1			T1	1		T3	5		T22	6
valid_sources[0x5f]	2448	1			T7	2		T56	3		T20	21
valid_sources[0x60]	2511	1			T25	1		T22	7		T20	17
valid_sources[0x61]	5385	1			T2	1		T7	1		T56	3
valid_sources[0x62]	2477	1			T25	2		T22	4		T20	17
valid_sources[0x63]	2509	1			T2	1		T4	11		T6	6
valid_sources[0x64]	2351	1			T4	24		T22	2		T20	15
valid_sources[0x65]	2394	1			T3	5		T4	12		T5	1
valid_sources[0x66]	3201	1			T56	2		T22	3		T20	25
valid_sources[0x67]	3321	1			T4	11		T5	1		T7	3
valid_sources[0x68]	3555	1			T4	11		T56	3		T22	1
valid_sources[0x69]	3505	1			T2	2		T3	3		T4	22
valid_sources[0x6a]	2152	1			T4	11		T7	8		T25	1
valid_sources[0x6b]	2537	1			T2	1		T38	1		T20	28
valid_sources[0x6c]	2563	1			T7	1		T38	3		T20	19
valid_sources[0x6d]	2310	1			T1	1		T3	1		T25	2
valid_sources[0x6e]	2399	1			T22	4		T20	20		T59	1
valid_sources[0x6f]	3260	1			T2	1		T38	2		T56	1
valid_sources[0x70]	3990	1			T1	3		T2	1		T4	11
valid_sources[0x71]	2430	1			T2	24		T4	11		T25	3
valid_sources[0x72]	3439	1			T4	595		T20	13		T24	1
valid_sources[0x73]	2703	1			T2	2		T4	22		T25	1
valid_sources[0x74]	2616	1			T2	1		T4	23		T5	1
valid_sources[0x75]	4042	1			T2	7		T4	11		T7	1
valid_sources[0x76]	2497	1			T4	11		T56	3		T22	10
valid_sources[0x77]	2504	1			T2	1		T4	11		T25	3
valid_sources[0x78]	3749	1			T4	1163		T25	3		T56	2
valid_sources[0x79]	4813	1			T2	1		T7	2		T13	13
valid_sources[0x7a]	2393	1			T25	1		T56	1		T22	1
valid_sources[0x7b]	2675	1			T4	12		T22	10		T20	23
valid_sources[0x7c]	3389	1			T2	1		T4	12		T56	1
valid_sources[0x7d]	4058	1			T4	1485		T5	2		T25	2
valid_sources[0x7e]	2249	1			T4	12		T5	3		T25	1
valid_sources[0x7f]	2282	1			T4	11		T5	2		T25	1
valid_sources[0x80]	3594	1			T2	12		T3	1		T4	1369

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

97481

1

T1

13

T2

41

T3

39

values[0x0]

all_enables

biggest_size

63871

1

T1

9

T2

35

T3

10

values[0x1]

all_enables

biggest_size

34610

1

T1

4

T2

13

T3

1