SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34223 | 1 | T22 | 289 | T23 | 294 | T24 | 296 | ||||
others[1] | 34398 | 1 | T22 | 308 | T23 | 286 | T24 | 300 | ||||
others[2] | 34456 | 1 | T22 | 273 | T23 | 304 | T24 | 321 | ||||
others[3] | 57620 | 1 | T22 | 532 | T23 | 515 | T24 | 489 | ||||
false | 19761 | 1 | T2 | 40 | T4 | 460 | T25 | 30 | ||||
true | 29966 | 1 | T1 | 1 | T2 | 41 | T3 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34284 | 1 | T22 | 294 | T23 | 272 | T24 | 310 | ||||
others[1] | 34444 | 1 | T22 | 291 | T23 | 309 | T24 | 273 | ||||
others[2] | 34365 | 1 | T22 | 301 | T23 | 302 | T24 | 297 | ||||
others[3] | 57600 | 1 | T22 | 527 | T23 | 515 | T24 | 513 | ||||
false | 12441 | 1 | T2 | 20 | T4 | 230 | T25 | 15 | ||||
true | 22707 | 1 | T1 | 1 | T2 | 21 | T3 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 703 | 1 | T1 | 7 | T3 | 2 | T4 | 10 | ||||
others[1] | 741 | 1 | T1 | 5 | T3 | 1 | T4 | 15 | ||||
others[2] | 694 | 1 | T1 | 2 | T4 | 5 | T37 | 1 | ||||
others[3] | 1181 | 1 | T1 | 10 | T4 | 25 | T5 | 2 | ||||
false | 14307 | 1 | T1 | 4 | T2 | 1 | T3 | 19 | ||||
true | 4419 | 1 | T1 | 1 | T3 | 4 | T4 | 96 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |