Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24585880	14909	0	0
intr_enable_rd_A	24585880	48627	0	0
reset_en_rd_A	24585880	2012	0	0
reset_en_regwen_rd_A	24585880	1619	0	0
wake_info_capture_dis_rd_A	24585880	1769	0	0
wakeup_en_rd_A	24585880	2964	0	0
wakeup_en_regwen_rd_A	24585880	1671	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24585880	14909	0	0
T4	390351	5	0	0
T5	2784	0	0	0
T6	1392	0	0	0
T7	19806	0	0	0
T8	682	0	0	0
T9	1059	0	0	0
T10	952	0	0	0
T13	1151	0	0	0
T20	0	4	0	0
T21	0	9	0	0
T38	1390	0	0	0
T41	1812	0	0	0
T42	0	1	0	0
T51	0	15	0	0
T85	0	57	0	0
T86	0	127	0	0
T133	0	42	0	0
T134	0	69	0	0
T135	0	72	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24585880	48627	0	0
T4	390351	3900	0	0
T5	2784	0	0	0
T6	1392	19	0	0
T7	19806	79	0	0
T8	682	0	0	0
T9	1059	0	0	0
T10	952	0	0	0
T13	1151	15	0	0
T25	0	39	0	0
T38	1390	0	0	0
T41	1812	0	0	0
T56	0	59	0	0
T59	0	36	0	0
T136	0	9	0	0
T137	0	10	0	0
T138	0	96	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24585880	2012	0	0
T4	390351	2	0	0
T5	2784	0	0	0
T6	1392	0	0	0
T7	19806	0	0	0
T8	682	0	0	0
T9	1059	0	0	0
T10	952	0	0	0
T13	1151	0	0	0
T38	1390	0	0	0
T41	1812	0	0	0
T42	0	7	0	0
T72	0	6	0	0
T77	0	7	0	0
T85	0	2	0	0
T93	0	4	0	0
T139	0	10	0	0
T140	0	5	0	0
T141	0	2	0	0
T142	0	4	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24585880	1619	0	0
T4	390351	2	0	0
T5	2784	0	0	0
T6	1392	0	0	0
T7	19806	0	0	0
T8	682	0	0	0
T9	1059	0	0	0
T10	952	0	0	0
T13	1151	0	0	0
T38	1390	0	0	0
T41	1812	0	0	0
T42	0	2	0	0
T72	0	11	0	0
T77	0	6	0	0
T85	0	6	0	0
T93	0	5	0	0
T139	0	10	0	0
T140	0	1	0	0
T142	0	7	0	0
T143	0	4	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24585880	1769	0	0
T4	390351	10	0	0
T5	2784	0	0	0
T6	1392	0	0	0
T7	19806	0	0	0
T8	682	0	0	0
T9	1059	0	0	0
T10	952	0	0	0
T13	1151	0	0	0
T38	1390	0	0	0
T41	1812	0	0	0
T42	0	7	0	0
T72	0	14	0	0
T77	0	4	0	0
T85	0	2	0	0
T93	0	2	0	0
T139	0	5	0	0
T141	0	3	0	0
T142	0	5	0	0
T143	0	20	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24585880	2964	0	0
T4	390351	3	0	0
T5	2784	0	0	0
T6	1392	0	0	0
T7	19806	0	0	0
T8	682	0	0	0
T9	1059	0	0	0
T10	952	0	0	0
T13	1151	0	0	0
T38	1390	0	0	0
T41	1812	0	0	0
T42	0	8	0	0
T72	0	1	0	0
T77	0	4	0	0
T85	0	4	0	0
T93	0	10	0	0
T140	0	2	0	0
T141	0	2	0	0
T142	0	13	0	0
T144	0	8	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24585880	1671	0	0
T4	390351	4	0	0
T5	2784	0	0	0
T6	1392	0	0	0
T7	19806	0	0	0
T8	682	0	0	0
T9	1059	0	0	0
T10	952	0	0	0
T13	1151	0	0	0
T38	1390	0	0	0
T41	1812	0	0	0
T42	0	5	0	0
T72	0	1	0	0
T77	0	8	0	0
T85	0	10	0	0
T93	0	7	0	0
T142	0	2	0	0
T143	0	4	0	0
T144	0	5	0	0
T145	0	1	0	0