Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	71998479	149411	0	0
StatusRise_A	71998479	166876	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71998479	149411	0	0
T1	19050	3	0	0
T2	60429	83	0	0
T3	9186	54	0	0
T4	1171053	3496	0	0
T5	8352	54	0	0
T6	4176	15	0	0
T7	59418	49	0	0
T8	2046	3	0	0
T9	3177	0	0	0
T10	2856	0	0	0
T13	0	6	0	0
T38	0	12	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71998479	166876	0	0
T1	19050	6	0	0
T2	60429	86	0	0
T3	9186	57	0	0
T4	1171053	3870	0	0
T5	8352	60	0	0
T6	4176	18	0	0
T7	59418	51	0	0
T8	2046	9	0	0
T9	3177	12	0	0
T10	2856	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23999493	55443	0	0
StatusRise_A	23999493	61737	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23999493	55443	0	0
T1	6350	1	0	0
T2	20143	33	0	0
T3	3062	18	0	0
T4	390351	1300	0	0
T5	2784	18	0	0
T6	1392	5	0	0
T7	19806	18	0	0
T8	682	1	0	0
T9	1059	0	0	0
T10	952	0	0	0
T13	0	2	0	0
T38	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23999493	61737	0	0
T1	6350	2	0	0
T2	20143	34	0	0
T3	3062	19	0	0
T4	390351	1436	0	0
T5	2784	20	0	0
T6	1392	6	0	0
T7	19806	19	0	0
T8	682	3	0	0
T9	1059	4	0	0
T10	952	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23999493	55443	0	0
StatusRise_A	23999493	61737	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23999493	55443	0	0
T1	6350	1	0	0
T2	20143	33	0	0
T3	3062	18	0	0
T4	390351	1300	0	0
T5	2784	18	0	0
T6	1392	5	0	0
T7	19806	18	0	0
T8	682	1	0	0
T9	1059	0	0	0
T10	952	0	0	0
T13	0	2	0	0
T38	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23999493	61737	0	0
T1	6350	2	0	0
T2	20143	34	0	0
T3	3062	19	0	0
T4	390351	1436	0	0
T5	2784	20	0	0
T6	1392	6	0	0
T7	19806	19	0	0
T8	682	3	0	0
T9	1059	4	0	0
T10	952	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	23999493	38525	0	0
StatusRise_A	23999493	43402	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23999493	38525	0	0
T1	6350	1	0	0
T2	20143	17	0	0
T3	3062	18	0	0
T4	390351	896	0	0
T5	2784	18	0	0
T6	1392	5	0	0
T7	19806	13	0	0
T8	682	1	0	0
T9	1059	0	0	0
T10	952	0	0	0
T13	0	2	0	0
T38	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23999493	43402	0	0
T1	6350	2	0	0
T2	20143	18	0	0
T3	3062	19	0	0
T4	390351	998	0	0
T5	2784	20	0	0
T6	1392	6	0	0
T7	19806	13	0	0
T8	682	3	0	0
T9	1059	4	0	0
T10	952	2	0	0