Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	24000098	5504	0	0
EscTimeoutStoppedByClReset_A	23999493	3292882	0	0
EscTimeoutTriggersReset_A	5193465	339	0	0
RomAllowActiveState_A	23999493	61335	0	0
RomAllowCheckGoodState_A	23999493	61388	0	0
RomBlockActiveState_A	23999493	31401	0	0
RomBlockCheckGoodState_A	23999493	424844	0	0
RomIntgChkDisFalse_A	23999493	23323488	0	0
RomIntgChkDisTrue_A	23999493	139032	0	0
RstreqChkEsctimeout_A	23999493	4670	0	0
RstreqChkFsmterm_A	23999493	140	0	0
RstreqChkGlbesc_A	23999493	4670	0	0
RstreqChkMainpd_A	23999493	977004	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24000098	5504	0	0
T11	15021	13	0	0
T12	15043	55	0	0
T14	1929	0	0	0
T20	121969	0	0	0
T22	10869	0	0	0
T23	19916	0	0	0
T31	0	186	0	0
T34	0	122	0	0
T35	0	144	0	0
T37	9757	0	0	0
T39	1126	11	0	0
T40	0	51	0	0
T59	4401	0	0	0
T84	5934	0	0	0
T97	0	32	0	0
T146	0	2	0	0
T147	0	116	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23999493	3292882	0	0
T1	6350	11	0	0
T2	20143	6654	0	0
T3	3062	330	0	0
T4	390351	32730	0	0
T5	2784	301	0	0
T6	1392	0	0	0
T7	19806	4827	0	0
T8	682	19	0	0
T9	1059	24	0	0
T10	952	24	0	0
T38	0	64	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5193465	339	0	0
T8	336	4	0	0
T9	414	0	0	0
T10	868	0	0	0
T11	1338	2	0	0
T12	0	3	0	0
T13	181	0	0	0
T14	351	0	0	0
T25	3150	0	0	0
T31	0	3	0	0
T34	0	3	0	0
T35	0	2	0	0
T38	483	0	0	0
T39	0	4	0	0
T40	0	3	0	0
T41	163	0	0	0
T56	3251	0	0	0
T97	0	2	0	0
T99	0	11	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23999493	61335	0	0
T1	6350	2	0	0
T2	20143	34	0	0
T3	3062	12	0	0
T4	390351	1436	0	0
T5	2784	13	0	0
T6	1392	6	0	0
T7	19806	19	0	0
T8	682	3	0	0
T9	1059	4	0	0
T10	952	2	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23999493	61388	0	0
T1	6350	2	0	0
T2	20143	34	0	0
T3	3062	13	0	0
T4	390351	1436	0	0
T5	2784	14	0	0
T6	1392	6	0	0
T7	19806	19	0	0
T8	682	3	0	0
T9	1059	4	0	0
T10	952	2	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23999493	31401	0	0
T20	121968	0	0	0
T23	19916	14	0	0
T24	45927	0	0	0
T39	1126	0	0	0
T46	0	11	0	0
T47	0	12	0	0
T59	4400	0	0	0
T81	16940	0	0	0
T82	1838	0	0	0
T83	1680	0	0	0
T136	907	0	0	0
T148	0	20	0	0
T149	0	22	0	0
T150	0	35	0	0
T151	0	1422	0	0
T152	0	17	0	0
T153	0	1064	0	0
T154	0	593	0	0
T155	1987	0	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23999493	424844	0	0
T2	20143	458	0	0
T3	3062	0	0	0
T4	390351	5274	0	0
T5	2784	0	0	0
T6	1392	0	0	0
T7	19806	0	0	0
T8	682	0	0	0
T9	1059	0	0	0
T10	952	0	0	0
T20	0	1536	0	0
T21	0	3314	0	0
T22	0	773	0	0
T23	0	1141	0	0
T24	0	4032	0	0
T25	0	344	0	0
T38	1390	0	0	0
T81	0	368	0	0
T156	0	252	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23999493	23323488	0	0
T1	6350	6259	0	0
T2	20143	20054	0	0
T3	3062	2152	0	0
T4	390351	380518	0	0
T5	2784	1856	0	0
T6	1392	1293	0	0
T7	19806	19711	0	0
T8	682	538	0	0
T9	1059	746	0	0
T10	952	792	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23999493	139032	0	0
T12	15042	0	0	0
T20	121968	0	0	0
T22	10868	118	0	0
T23	19916	328	0	0
T24	45927	1781	0	0
T28	0	1938	0	0
T37	9757	0	0	0
T39	1126	0	0	0
T59	4400	0	0	0
T84	5933	0	0	0
T151	0	377	0	0
T155	1987	0	0	0
T157	0	762	0	0
T158	0	1591	0	0
T159	0	2495	0	0
T160	0	2900	0	0
T161	0	617	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23999493	4670	0	0
T3	3062	7	0	0
T4	390351	96	0	0
T5	2784	7	0	0
T6	1392	0	0	0
T7	19806	0	0	0
T8	682	1	0	0
T9	1059	3	0	0
T10	952	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T20	0	38	0	0
T37	0	8	0	0
T38	1390	0	0	0
T41	1812	0	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23999493	140	0	0
T17	16912	40	0	0
T18	0	20	0	0
T19	0	40	0	0
T26	0	20	0	0
T27	0	20	0	0
T28	54680	0	0	0
T29	1669	0	0	0
T30	1960	0	0	0
T31	15506	0	0	0
T32	1976	0	0	0
T33	19388	0	0	0
T34	15194	0	0	0
T35	15462	0	0	0
T36	3685	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23999493	4670	0	0
T3	3062	7	0	0
T4	390351	96	0	0
T5	2784	7	0	0
T6	1392	0	0	0
T7	19806	0	0	0
T8	682	1	0	0
T9	1059	3	0	0
T10	952	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T20	0	38	0	0
T37	0	8	0	0
T38	1390	0	0	0
T41	1812	0	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23999493	977004	0	0
T2	20143	1429	0	0
T3	3062	170	0	0
T4	390351	6572	0	0
T5	2784	107	0	0
T6	1392	0	0	0
T7	19806	0	0	0
T8	682	0	0	0
T9	1059	0	0	0
T10	952	0	0	0
T14	0	17	0	0
T22	0	1021	0	0
T23	0	1113	0	0
T25	0	394	0	0
T37	0	482	0	0
T38	1390	0	0	0
T41	0	5	0	0