Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	568360	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

220069

1

T2

3421

T3

137

T4

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	417525	1			T1	1		T2	6530		T3	242
values[0x0]	185669	1			T2	2928		T3	14		T4	28
values[0x1]	185235	1			T2	2992		T3	19		T4	28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	450137	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

338292

1

T1

1

T2

5377

T3

165

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4348	1			T2	54		T3	1		T6	8
valid_sources[0x01]	3222	1			T2	50		T5	8		T9	3
valid_sources[0x02]	4166	1			T2	68		T3	7		T9	3
valid_sources[0x03]	8236	1			T2	40		T9	4		T20	1
valid_sources[0x04]	2774	1			T2	55		T3	1		T9	2
valid_sources[0x05]	2276	1			T2	52		T4	1		T9	4
valid_sources[0x06]	2513	1			T2	21		T3	1		T9	5
valid_sources[0x07]	2955	1			T2	53		T4	2		T9	3
valid_sources[0x08]	2340	1			T2	54		T3	1		T5	2
valid_sources[0x09]	3279	1			T2	51		T9	3		T20	1
valid_sources[0x0a]	3803	1			T2	76		T3	2		T4	1
valid_sources[0x0b]	2386	1			T2	47		T3	2		T4	1
valid_sources[0x0c]	2787	1			T2	46		T9	6		T20	1
valid_sources[0x0d]	3539	1			T2	60		T9	3		T12	29
valid_sources[0x0e]	2408	1			T2	51		T3	4		T9	4
valid_sources[0x0f]	2778	1			T2	49		T3	3		T4	2
valid_sources[0x10]	3427	1			T2	56		T9	3		T59	2
valid_sources[0x11]	2276	1			T2	40		T3	2		T9	4
valid_sources[0x12]	3459	1			T2	68		T3	1		T4	1
valid_sources[0x13]	2576	1			T2	57		T3	3		T5	4
valid_sources[0x14]	2258	1			T2	48		T3	5		T9	2
valid_sources[0x15]	3595	1			T2	44		T3	1		T5	1
valid_sources[0x16]	2736	1			T2	43		T4	1		T9	2
valid_sources[0x17]	2802	1			T2	22		T4	1		T6	3
valid_sources[0x18]	2248	1			T2	49		T3	2		T4	1
valid_sources[0x19]	4003	1			T2	43		T6	24		T9	2
valid_sources[0x1a]	3036	1			T2	49		T9	8		T127	1
valid_sources[0x1b]	3306	1			T2	57		T9	3		T34	2
valid_sources[0x1c]	4313	1			T2	53		T3	1		T5	2
valid_sources[0x1d]	2821	1			T2	78		T3	1		T9	2
valid_sources[0x1e]	2308	1			T2	50		T3	1		T5	1
valid_sources[0x1f]	4774	1			T2	33		T4	2		T9	3
valid_sources[0x20]	2934	1			T2	42		T4	1		T5	1
valid_sources[0x21]	3191	1			T2	51		T3	1		T5	1
valid_sources[0x22]	4786	1			T2	33		T4	1		T9	1
valid_sources[0x23]	3596	1			T2	39		T6	1		T9	6
valid_sources[0x24]	2450	1			T2	70		T3	2		T9	7
valid_sources[0x25]	2900	1			T2	83		T3	2		T4	1
valid_sources[0x26]	2502	1			T2	56		T3	1		T4	1
valid_sources[0x27]	2329	1			T2	72		T3	3		T9	5
valid_sources[0x28]	3245	1			T2	48		T9	2		T127	2
valid_sources[0x29]	2805	1			T2	54		T3	3		T9	2
valid_sources[0x2a]	2774	1			T2	42		T5	5		T9	2
valid_sources[0x2b]	2238	1			T2	83		T3	1		T12	29
valid_sources[0x2c]	4031	1			T2	42		T3	2		T9	4
valid_sources[0x2d]	3583	1			T2	46		T3	2		T9	3
valid_sources[0x2e]	2449	1			T2	82		T3	2		T5	3
valid_sources[0x2f]	2893	1			T2	52		T3	1		T4	3
valid_sources[0x30]	3124	1			T2	38		T9	4		T59	4
valid_sources[0x31]	2652	1			T2	49		T3	3		T4	1
valid_sources[0x32]	3098	1			T2	42		T3	1		T4	1
valid_sources[0x33]	2521	1			T2	61		T3	2		T4	1
valid_sources[0x34]	12455	1			T2	73		T3	4		T9	4
valid_sources[0x35]	4206	1			T2	58		T5	1		T12	28
valid_sources[0x36]	3066	1			T2	36		T3	2		T5	3
valid_sources[0x37]	3007	1			T2	34		T9	3		T20	1
valid_sources[0x38]	3273	1			T2	63		T3	2		T9	4
valid_sources[0x39]	3729	1			T2	32		T3	1		T6	5
valid_sources[0x3a]	3291	1			T2	70		T9	3		T34	1
valid_sources[0x3b]	3358	1			T2	42		T3	2		T5	3
valid_sources[0x3c]	2611	1			T2	29		T3	1		T9	8
valid_sources[0x3d]	2943	1			T2	32		T3	1		T4	1
valid_sources[0x3e]	2782	1			T2	53		T9	1		T59	3
valid_sources[0x3f]	2393	1			T2	44		T6	2		T9	4
valid_sources[0x40]	4291	1			T2	83		T9	2		T10	1
valid_sources[0x41]	2589	1			T2	28		T3	1		T12	30
valid_sources[0x42]	4254	1			T2	62		T3	1		T9	5
valid_sources[0x43]	4349	1			T2	63		T5	4		T9	3
valid_sources[0x44]	2299	1			T2	63		T9	2		T38	1
valid_sources[0x45]	2785	1			T2	36		T6	33		T9	1
valid_sources[0x46]	4157	1			T2	32		T3	3		T9	1
valid_sources[0x47]	2335	1			T2	47		T5	1		T6	10
valid_sources[0x48]	4162	1			T2	40		T3	1		T9	6
valid_sources[0x49]	3386	1			T2	26		T4	1		T9	1
valid_sources[0x4a]	2335	1			T2	33		T9	6		T59	4
valid_sources[0x4b]	2476	1			T2	53		T3	3		T6	14
valid_sources[0x4c]	3381	1			T2	26		T3	1		T5	1
valid_sources[0x4d]	2695	1			T2	33		T9	1		T127	7
valid_sources[0x4e]	2740	1			T2	43		T3	1		T9	2
valid_sources[0x4f]	3776	1			T2	47		T3	2		T5	4
valid_sources[0x50]	3037	1			T2	35		T9	2		T127	4
valid_sources[0x51]	2965	1			T2	45		T4	1		T9	9
valid_sources[0x52]	2277	1			T2	56		T4	1		T9	3
valid_sources[0x53]	2554	1			T2	38		T3	2		T9	7
valid_sources[0x54]	2397	1			T2	49		T3	5		T9	5
valid_sources[0x55]	2449	1			T2	56		T5	4		T9	2
valid_sources[0x56]	3289	1			T2	51		T9	1		T34	1
valid_sources[0x57]	2392	1			T2	49		T3	2		T9	2
valid_sources[0x58]	2463	1			T2	37		T9	1		T34	3
valid_sources[0x59]	2648	1			T2	36		T3	1		T9	3
valid_sources[0x5a]	3029	1			T2	32		T3	1		T4	1
valid_sources[0x5b]	2719	1			T2	81		T6	1		T9	3
valid_sources[0x5c]	2730	1			T2	55		T3	1		T5	1
valid_sources[0x5d]	3584	1			T2	84		T3	2		T5	1
valid_sources[0x5e]	3237	1			T2	53		T4	3		T6	8
valid_sources[0x5f]	3091	1			T2	48		T9	4		T12	20
valid_sources[0x60]	3625	1			T2	53		T3	1		T4	1
valid_sources[0x61]	2263	1			T2	55		T3	1		T4	1
valid_sources[0x62]	3229	1			T2	29		T4	1		T6	4
valid_sources[0x63]	5172	1			T2	42		T3	2		T4	1
valid_sources[0x64]	3276	1			T2	63		T4	1		T6	6
valid_sources[0x65]	3089	1			T2	46		T3	2		T9	3
valid_sources[0x66]	3947	1			T2	68		T6	9		T9	1
valid_sources[0x67]	4024	1			T2	62		T3	1		T4	1
valid_sources[0x68]	2289	1			T2	24		T4	1		T9	1
valid_sources[0x69]	2912	1			T2	74		T5	6		T9	3
valid_sources[0x6a]	2539	1			T2	30		T3	2		T9	3
valid_sources[0x6b]	2229	1			T2	38		T4	2		T9	3
valid_sources[0x6c]	3824	1			T2	40		T3	1		T4	2
valid_sources[0x6d]	2653	1			T2	32		T3	1		T4	2
valid_sources[0x6e]	2371	1			T2	63		T3	4		T9	1
valid_sources[0x6f]	4697	1			T2	72		T3	2		T5	1
valid_sources[0x70]	3158	1			T2	39		T4	1		T9	2
valid_sources[0x71]	3148	1			T2	70		T3	1		T9	3
valid_sources[0x72]	2346	1			T2	53		T4	2		T9	3
valid_sources[0x73]	2897	1			T2	43		T9	1		T59	4
valid_sources[0x74]	3468	1			T2	85		T34	1		T12	26
valid_sources[0x75]	2657	1			T2	34		T3	2		T9	1
valid_sources[0x76]	4839	1			T2	48		T4	1		T9	8
valid_sources[0x77]	2659	1			T2	52		T4	1		T9	4
valid_sources[0x78]	2428	1			T2	22		T4	3		T9	4
valid_sources[0x79]	2587	1			T2	36		T4	2		T9	5
valid_sources[0x7a]	3287	1			T2	30		T3	2		T36	3
valid_sources[0x7b]	2721	1			T2	34		T4	1		T6	2
valid_sources[0x7c]	2662	1			T2	35		T6	1		T9	2
valid_sources[0x7d]	2732	1			T2	49		T3	3		T9	3
valid_sources[0x7e]	2438	1			T2	52		T9	3		T34	1
valid_sources[0x7f]	2649	1			T2	51		T4	3		T9	3
valid_sources[0x80]	2253	1			T2	74		T3	6		T6	30

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

114691

1

T2

1772

T3

130

T4

11

values[0x0]

all_enables

biggest_size

68706

1

T2

1081

T3

5

T4

9

values[0x1]

all_enables

biggest_size

36672

1

T2

568

T3

2

T4

2