SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34232 | 1 | T8 | 368 | T9 | 276 | T33 | 408 | ||||
others[1] | 34577 | 1 | T8 | 406 | T9 | 294 | T33 | 415 | ||||
others[2] | 34405 | 1 | T8 | 416 | T9 | 324 | T33 | 388 | ||||
others[3] | 57561 | 1 | T8 | 677 | T9 | 515 | T33 | 642 | ||||
false | 21050 | 1 | T2 | 252 | T8 | 50 | T9 | 50 | ||||
true | 31669 | 1 | T1 | 2 | T2 | 350 | T3 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34411 | 1 | T8 | 400 | T9 | 300 | T33 | 397 | ||||
others[1] | 34212 | 1 | T8 | 396 | T9 | 282 | T33 | 394 | ||||
others[2] | 34446 | 1 | T8 | 359 | T9 | 315 | T33 | 390 | ||||
others[3] | 57512 | 1 | T8 | 736 | T9 | 503 | T33 | 690 | ||||
false | 13065 | 1 | T2 | 126 | T8 | 50 | T9 | 50 | ||||
true | 23749 | 1 | T1 | 2 | T2 | 224 | T3 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 711 | 1 | T2 | 7 | T5 | 1 | T7 | 5 | ||||
others[1] | 704 | 1 | T2 | 8 | T3 | 1 | T5 | 3 | ||||
others[2] | 702 | 1 | T2 | 5 | T7 | 6 | T59 | 4 | ||||
others[3] | 1230 | 1 | T2 | 12 | T3 | 1 | T5 | 3 | ||||
false | 14521 | 1 | T1 | 2 | T2 | 195 | T3 | 20 | ||||
true | 4182 | 1 | T2 | 65 | T3 | 6 | T5 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |