Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	26956810	14692	0	0
intr_enable_rd_A	26956810	47617	0	0
reset_en_rd_A	26956810	1567	0	0
reset_en_regwen_rd_A	26956810	1317	0	0
wake_info_capture_dis_rd_A	26956810	1275	0	0
wakeup_en_rd_A	26956810	2709	0	0
wakeup_en_regwen_rd_A	26956810	1214	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26956810	14692	0	0
T2	221840	30	0	0
T3	5619	0	0	0
T4	5263	0	0	0
T5	4423	0	0	0
T6	2497	0	0	0
T7	7137	0	0	0
T8	62836	0	0	0
T9	18715	0	0	0
T10	2201	0	0	0
T12	0	64	0	0
T19	0	38	0	0
T36	1456	0	0	0
T45	0	16	0	0
T48	0	20	0	0
T73	0	5	0	0
T76	0	28	0	0
T124	0	20	0	0
T125	0	30	0	0
T126	0	71	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26956810	47617	0	0
T4	5263	14	0	0
T5	4423	51	0	0
T6	2497	0	0	0
T7	7137	113	0	0
T8	62836	184	0	0
T9	18715	172	0	0
T10	2201	0	0	0
T11	15247	0	0	0
T34	0	23	0	0
T36	1456	0	0	0
T59	7231	61	0	0
T78	0	8	0	0
T92	0	24	0	0
T127	0	106	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26956810	1567	0	0
T14	1331	0	0	0
T15	1258	0	0	0
T43	1698	0	0	0
T45	492346	0	0	0
T48	477073	8	0	0
T87	0	6	0	0
T93	0	14	0	0
T119	2716	0	0	0
T128	0	9	0	0
T129	0	1	0	0
T130	0	18	0	0
T131	0	8	0	0
T132	0	1	0	0
T133	0	24	0	0
T134	0	13	0	0
T135	4054	0	0	0
T136	2518	0	0	0
T137	5326	0	0	0
T138	4128	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26956810	1317	0	0
T14	1331	0	0	0
T15	1258	0	0	0
T43	1698	0	0	0
T45	492346	0	0	0
T48	477073	4	0	0
T87	0	6	0	0
T88	0	1	0	0
T93	0	32	0	0
T119	2716	0	0	0
T128	0	1	0	0
T129	0	10	0	0
T130	0	29	0	0
T131	0	13	0	0
T132	0	3	0	0
T133	0	16	0	0
T135	4054	0	0	0
T136	2518	0	0	0
T137	5326	0	0	0
T138	4128	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26956810	1275	0	0
T14	1331	0	0	0
T15	1258	0	0	0
T43	1698	0	0	0
T45	492346	0	0	0
T48	477073	7	0	0
T87	0	3	0	0
T93	0	6	0	0
T119	2716	0	0	0
T128	0	6	0	0
T129	0	4	0	0
T130	0	15	0	0
T131	0	2	0	0
T132	0	1	0	0
T133	0	17	0	0
T134	0	7	0	0
T135	4054	0	0	0
T136	2518	0	0	0
T137	5326	0	0	0
T138	4128	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26956810	2709	0	0
T14	1331	0	0	0
T15	1258	0	0	0
T43	1698	0	0	0
T45	492346	0	0	0
T48	477073	4	0	0
T87	0	6	0	0
T93	0	31	0	0
T119	2716	0	0	0
T128	0	5	0	0
T129	0	9	0	0
T130	0	14	0	0
T131	0	15	0	0
T132	0	9	0	0
T133	0	8	0	0
T134	0	4	0	0
T135	4054	0	0	0
T136	2518	0	0	0
T137	5326	0	0	0
T138	4128	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26956810	1214	0	0
T14	1331	0	0	0
T15	1258	0	0	0
T43	1698	0	0	0
T45	492346	0	0	0
T48	477073	9	0	0
T87	0	2	0	0
T93	0	19	0	0
T119	2716	0	0	0
T128	0	4	0	0
T129	0	3	0	0
T130	0	17	0	0
T131	0	10	0	0
T132	0	1	0	0
T133	0	17	0	0
T134	0	6	0	0
T135	4054	0	0	0
T136	2518	0	0	0
T137	5326	0	0	0
T138	4128	0	0	0