Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	79038072	159316	0	0
StatusRise_A	79038072	177628	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79038072	159316	0	0
T1	1437	3	0	0
T2	665520	2490	0	0
T3	16857	54	0	0
T4	15789	18	0	0
T5	13269	48	0	0
T6	7491	32	0	0
T7	21411	3	0	0
T8	188508	219	0	0
T9	56145	226	0	0
T10	6603	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79038072	177628	0	0
T1	1437	9	0	0
T2	665520	2758	0	0
T3	16857	57	0	0
T4	15789	20	0	0
T5	13269	54	0	0
T6	7491	35	0	0
T7	21411	6	0	0
T8	188508	225	0	0
T9	56145	229	0	0
T10	6603	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	26346024	59099	0	0
StatusRise_A	26346024	65730	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26346024	59099	0	0
T1	479	1	0	0
T2	221840	921	0	0
T3	5619	18	0	0
T4	5263	8	0	0
T5	4423	16	0	0
T6	2497	13	0	0
T7	7137	1	0	0
T8	62836	88	0	0
T9	18715	87	0	0
T10	2201	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26346024	65730	0	0
T1	479	3	0	0
T2	221840	1019	0	0
T3	5619	19	0	0
T4	5263	9	0	0
T5	4423	18	0	0
T6	2497	14	0	0
T7	7137	2	0	0
T8	62836	90	0	0
T9	18715	88	0	0
T10	2201	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	26346024	59099	0	0
StatusRise_A	26346024	65732	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26346024	59099	0	0
T1	479	1	0	0
T2	221840	921	0	0
T3	5619	18	0	0
T4	5263	8	0	0
T5	4423	16	0	0
T6	2497	13	0	0
T7	7137	1	0	0
T8	62836	88	0	0
T9	18715	87	0	0
T10	2201	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26346024	65732	0	0
T1	479	3	0	0
T2	221840	1019	0	0
T3	5619	19	0	0
T4	5263	9	0	0
T5	4423	18	0	0
T6	2497	14	0	0
T7	7137	2	0	0
T8	62836	90	0	0
T9	18715	88	0	0
T10	2201	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	26346024	41118	0	0
StatusRise_A	26346024	46166	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26346024	41118	0	0
T1	479	1	0	0
T2	221840	648	0	0
T3	5619	18	0	0
T4	5263	2	0	0
T5	4423	16	0	0
T6	2497	6	0	0
T7	7137	1	0	0
T8	62836	43	0	0
T9	18715	52	0	0
T10	2201	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26346024	46166	0	0
T1	479	3	0	0
T2	221840	720	0	0
T3	5619	19	0	0
T4	5263	2	0	0
T5	4423	18	0	0
T6	2497	7	0	0
T7	7137	2	0	0
T8	62836	45	0	0
T9	18715	53	0	0
T10	2201	3	0	0