Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	26346606	5399	0	0
EscTimeoutStoppedByClReset_A	26346024	3707020	0	0
EscTimeoutTriggersReset_A	5446144	309	0	0
RomAllowActiveState_A	26346024	65323	0	0
RomAllowCheckGoodState_A	26346024	65374	0	0
RomBlockActiveState_A	26346024	30439	0	0
RomBlockCheckGoodState_A	26346024	444406	0	0
RomIntgChkDisFalse_A	26346024	25623314	0	0
RomIntgChkDisTrue_A	26346024	158257	0	0
RstreqChkEsctimeout_A	26346024	4522	0	0
RstreqChkFsmterm_A	26346024	160	0	0
RstreqChkGlbesc_A	26346024	4522	0	0
RstreqChkMainpd_A	26346024	1042944	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26346606	5399	0	0
T1	480	1	0	0
T2	221841	0	0	0
T3	5619	0	0	0
T4	5263	0	0	0
T5	4423	0	0	0
T6	2497	0	0	0
T7	7138	0	0	0
T8	62836	0	0	0
T9	18716	0	0	0
T10	2202	34	0	0
T11	0	63	0	0
T90	0	143	0	0
T139	0	21	0	0
T140	0	244	0	0
T141	0	5	0	0
T142	0	19	0	0
T143	0	10	0	0
T144	0	31	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26346024	3707020	0	0
T1	479	21	0	0
T2	221840	27974	0	0
T3	5619	270	0	0
T4	5263	1174	0	0
T5	4423	417	0	0
T6	2497	0	0	0
T7	7137	12	0	0
T8	62836	11436	0	0
T9	18715	2195	0	0
T10	2201	24	0	0
T36	0	11	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5446144	309	0	0
T1	713	16	0	0
T2	77057	0	0	0
T3	591	0	0	0
T4	1105	0	0	0
T5	671	0	0	0
T6	193	0	0	0
T7	540	0	0	0
T8	6379	0	0	0
T9	15312	0	0	0
T10	192	3	0	0
T11	0	2	0	0
T37	0	3	0	0
T38	0	3	0	0
T39	0	2	0	0
T90	0	2	0	0
T139	0	3	0	0
T140	0	3	0	0
T141	0	4	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26346024	65323	0	0
T1	479	3	0	0
T2	221840	1017	0	0
T3	5619	12	0	0
T4	5263	9	0	0
T5	4423	18	0	0
T6	2497	14	0	0
T7	7137	2	0	0
T8	62836	90	0	0
T9	18715	88	0	0
T10	2201	3	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26346024	65374	0	0
T1	479	3	0	0
T2	221840	1017	0	0
T3	5619	13	0	0
T4	5263	9	0	0
T5	4423	18	0	0
T6	2497	14	0	0
T7	7137	2	0	0
T8	62836	90	0	0
T9	18715	88	0	0
T10	2201	3	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26346024	30439	0	0
T9	18715	3	0	0
T10	2201	0	0	0
T11	15247	0	0	0
T20	0	753	0	0
T21	0	105	0	0
T33	15609	14	0	0
T36	1456	0	0	0
T37	1350	0	0	0
T38	2422	0	0	0
T39	2464	0	0	0
T59	7231	0	0	0
T78	2407	0	0	0
T85	0	12	0	0
T92	0	353	0	0
T145	0	658	0	0
T146	0	19	0	0
T147	0	144	0	0
T148	0	359	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26346024	444406	0	0
T2	221840	2892	0	0
T3	5619	0	0	0
T4	5263	0	0	0
T5	4423	0	0	0
T6	2497	0	0	0
T7	7137	0	0	0
T8	62836	4055	0	0
T9	18715	751	0	0
T10	2201	0	0	0
T12	0	1126	0	0
T19	0	6132	0	0
T20	0	334	0	0
T21	0	38	0	0
T33	0	1032	0	0
T34	0	251	0	0
T36	1456	0	0	0
T92	0	149	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26346024	25623314	0	0
T1	479	333	0	0
T2	221840	214754	0	0
T3	5619	4675	0	0
T4	5263	5167	0	0
T5	4423	4283	0	0
T6	2497	2433	0	0
T7	7137	7043	0	0
T8	62836	62712	0	0
T9	18715	18521	0	0
T10	2201	2043	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26346024	158257	0	0
T9	18715	132	0	0
T10	2201	0	0	0
T11	15247	0	0	0
T20	0	104	0	0
T21	0	152	0	0
T33	15609	0	0	0
T36	1456	0	0	0
T37	1350	0	0	0
T38	2422	0	0	0
T39	2464	0	0	0
T59	7231	0	0	0
T78	2407	0	0	0
T85	0	956	0	0
T92	0	269	0	0
T145	0	445	0	0
T146	0	634	0	0
T147	0	264	0	0
T149	0	88	0	0
T150	0	2583	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26346024	4522	0	0
T1	479	1	0	0
T2	221840	60	0	0
T3	5619	5	0	0
T4	5263	0	0	0
T5	4423	7	0	0
T6	2497	0	0	0
T7	7137	0	0	0
T8	62836	0	0	0
T9	18715	0	0	0
T10	2201	1	0	0
T11	0	1	0	0
T20	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26346024	160	0	0
T16	18110	40	0	0
T17	0	40	0	0
T18	0	40	0	0
T22	0	20	0	0
T23	0	20	0	0
T24	357833	0	0	0
T25	912	0	0	0
T26	54550	0	0	0
T27	25566	0	0	0
T28	2530	0	0	0
T29	41163	0	0	0
T30	2474	0	0	0
T31	311752	0	0	0
T32	6323	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26346024	4522	0	0
T1	479	1	0	0
T2	221840	60	0	0
T3	5619	5	0	0
T4	5263	0	0	0
T5	4423	7	0	0
T6	2497	0	0	0
T7	7137	0	0	0
T8	62836	0	0	0
T9	18715	0	0	0
T10	2201	1	0	0
T11	0	1	0	0
T20	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26346024	1042944	0	0
T2	221840	5990	0	0
T3	5619	0	0	0
T4	5263	0	0	0
T5	4423	392	0	0
T6	2497	0	0	0
T7	7137	0	0	0
T8	62836	5016	0	0
T9	18715	1015	0	0
T10	2201	0	0	0
T12	0	6574	0	0
T19	0	27149	0	0
T20	0	119	0	0
T21	0	64	0	0
T33	0	1925	0	0
T34	0	515	0	0
T36	1456	0	0	0