Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_wakeup_intr_cg_wrap::wakeup_intr_cg

Group : pwrmgr_env_pkg::pwrmgr_wakeup_intr_cg_wrap::wakeup_intr_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

6 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
WakeupAonTimer_intr_cg	100.00	1	100	1	64	64
WakeupDbgCable_intr_cg	100.00	1	100	1	64	64
WakeupPin_intr_cg	100.00	1	100	1	64	64
WakeupSensorCtrl_intr_cg	100.00	1	100	1	64	64
WakeupSysrst_intr_cg	100.00	1	100	1	64	64
WakeupUsb_intr_cg	100.00	1	100	1	64	64

---

Group Instance : WakeupAonTimer_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupAonTimer_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupAonTimer_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupAonTimer_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupDbgCable_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupDbgCable_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupDbgCable_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupDbgCable_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupPin_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupPin_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupPin_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupPin_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupSensorCtrl_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupSensorCtrl_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupSensorCtrl_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupSensorCtrl_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupSysrst_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupSysrst_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupSysrst_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupSysrst_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : WakeupUsb_intr_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance WakeupUsb_intr_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	8	0	8	100.00

Variables for Group Instance WakeupUsb_intr_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
interrupt_cp	2	0	2	100.00	100	1	1	2
status_cp	2	0	2	100.00	100	1	1	2
wakeup_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance WakeupUsb_intr_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
interrupt_cross	8	0	8	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50376

1

T1

5

T2

20

T3

6

auto[1]

12998

1

T1

11

T2

4

T4

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48097

1

T1

12

T2

12

T3

6

auto[1]

15277

1

T1

4

T2

12

T4

8

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34914

1

T1

12

T2

12

T3

6

auto[1]

28460

1

T1

4

T2

12

T4

8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26549

1

T1

1

T2

7

T3

6

auto[1]

36825

1

T1

15

T2

17

T4

16

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

15732

1

T1

1

T2

7

T3

6

auto[0]

auto[0]

auto[1]

auto[0]

12836

1

T1

3

T2

3

T4

3

auto[0]

auto[1]

auto[0]

auto[0]

8637

1

T5

1

T6

1

T8

72

auto[0]

auto[1]

auto[1]

auto[0]

3484

1

T7

5

T8

38

T16

4

auto[1]

auto[0]

auto[0]

auto[0]

1118

1

T8

14

T14

6

T23

4

auto[1]

auto[0]

auto[1]

auto[0]

5228

1

T1

8

T2

2

T4

5

auto[1]

auto[1]

auto[0]

auto[0]

1062

1

T8

6

T23

6

T38

4

auto[1]

auto[1]

auto[1]

auto[1]

5590

1

T1

3

T2

2

T4

4

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50354

1

T1

13

T2

17

T3

6

auto[1]

13020

1

T1

3

T2

7

T4

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48097

1

T1

12

T2

12

T3

6

auto[1]

15277

1

T1

4

T2

12

T4

8

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34914

1

T1

12

T2

12

T3

6

auto[1]

28460

1

T1

4

T2

12

T4

8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26549

1

T1

1

T2

7

T3

6

auto[1]

36825

1

T1

15

T2

17

T4

16

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

15738

1

T1

1

T2

3

T3

6

auto[0]

auto[0]

auto[1]

auto[0]

12848

1

T1

9

T2

3

T4

3

auto[0]

auto[1]

auto[0]

auto[0]

8559

1

T5

1

T6

1

T8

66

auto[0]

auto[1]

auto[1]

auto[0]

3484

1

T7

5

T8

38

T16

4

auto[1]

auto[0]

auto[0]

auto[0]

1112

1

T2

4

T8

14

T14

2

auto[1]

auto[0]

auto[1]

auto[0]

5216

1

T1

2

T2

2

T4

5

auto[1]

auto[1]

auto[0]

auto[0]

1140

1

T8

12

T14

4

T23

8

auto[1]

auto[1]

auto[1]

auto[1]

5552

1

T1

1

T2

1

T4

4

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50412

1

T1

9

T2

10

T3

6

auto[1]

12962

1

T1

7

T2

14

T4

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48097

1

T1

12

T2

12

T3

6

auto[1]

15277

1

T1

4

T2

12

T4

8

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34914

1

T1

12

T2

12

T3

6

auto[1]

28460

1

T1

4

T2

12

T4

8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26549

1

T1

1

T2

7

T3

6

auto[1]

36825

1

T1

15

T2

17

T4

16

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

15808

1

T1

1

T2

5

T3

6

auto[0]

auto[0]

auto[1]

auto[0]

12800

1

T1

6

T2

2

T4

3

auto[0]

auto[1]

auto[0]

auto[0]

8601

1

T5

1

T6

1

T8

74

auto[0]

auto[1]

auto[1]

auto[0]

3484

1

T7

5

T8

38

T16

4

auto[1]

auto[0]

auto[0]

auto[0]

1042

1

T2

2

T8

6

T14

4

auto[1]

auto[0]

auto[1]

auto[0]

5264

1

T1

5

T2

3

T4

5

auto[1]

auto[1]

auto[0]

auto[0]

1098

1

T8

4

T14

2

T23

6

auto[1]

auto[1]

auto[1]

auto[1]

5558

1

T1

2

T2

9

T4

4

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50119

1

T1

6

T2

18

T3

6

auto[1]

13255

1

T1

10

T2

6

T4

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48097

1

T1

12

T2

12

T3

6

auto[1]

15277

1

T1

4

T2

12

T4

8

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34914

1

T1

12

T2

12

T3

6

auto[1]

28460

1

T1

4

T2

12

T4

8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26549

1

T1

1

T2

7

T3

6

auto[1]

36825

1

T1

15

T2

17

T4

16

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

15758

1

T1

1

T2

7

T3

6

auto[0]

auto[0]

auto[1]

auto[0]

12686

1

T1

4

T2

3

T4

5

auto[0]

auto[1]

auto[0]

auto[0]

8674

1

T5

1

T6

1

T8

70

auto[0]

auto[1]

auto[1]

auto[0]

3484

1

T7

5

T8

38

T16

4

auto[1]

auto[0]

auto[0]

auto[0]

1092

1

T8

4

T14

4

T23

4

auto[1]

auto[0]

auto[1]

auto[0]

5378

1

T1

7

T2

2

T4

3

auto[1]

auto[1]

auto[0]

auto[0]

1025

1

T8

8

T14

4

T23

6

auto[1]

auto[1]

auto[1]

auto[1]

5760

1

T1

3

T2

4

T4

6

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50544

1

T1

3

T2

21

T3

6

auto[1]

12830

1

T1

13

T2

3

T4

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48097

1

T1

12

T2

12

T3

6

auto[1]

15277

1

T1

4

T2

12

T4

8

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34914

1

T1

12

T2

12

T3

6

auto[1]

28460

1

T1

4

T2

12

T4

8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26549

1

T1

1

T2

7

T3

6

auto[1]

36825

1

T1

15

T2

17

T4

16

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

15778

1

T1

1

T2

7

T3

6

auto[0]

auto[0]

auto[1]

auto[0]

12971

1

T2

5

T4

4

T7

7

auto[0]

auto[1]

auto[0]

auto[0]

8562

1

T5

1

T6

1

T8

72

auto[0]

auto[1]

auto[1]

auto[0]

3484

1

T7

5

T8

38

T16

4

auto[1]

auto[0]

auto[0]

auto[0]

1072

1

T8

6

T14

8

T23

2

auto[1]

auto[0]

auto[1]

auto[0]

5093

1

T1

11

T4

4

T8

30

auto[1]

auto[1]

auto[0]

auto[0]

1137

1

T8

6

T14

8

T23

6

auto[1]

auto[1]

auto[1]

auto[1]

5528

1

T1

2

T2

3

T4

2

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50317

1

T1

8

T2

19

T3

6

auto[1]

13057

1

T1

8

T2

5

T4

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48097

1

T1

12

T2

12

T3

6

auto[1]

15277

1

T1

4

T2

12

T4

8

---

Summary for Variable status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for status_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34914

1

T1

12

T2

12

T3

6

auto[1]

28460

1

T1

4

T2

12

T4

8

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26549

1

T1

1

T2

7

T3

6

auto[1]

36825

1

T1

15

T2

17

T4

16

---

Summary for Cross interrupt_cross

Samples crossed: enable_cp status_cp wakeup_cp interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for interrupt_cross

Bins

enable_cp

status_cp

wakeup_cp

interrupt_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

15763

1

T1

1

T2

5

T3

6

auto[0]

auto[0]

auto[1]

auto[0]

12830

1

T1

4

T2

3

T4

5

auto[0]

auto[1]

auto[0]

auto[0]

8599

1

T5

1

T6

1

T8

70

auto[0]

auto[1]

auto[1]

auto[0]

3484

1

T7

5

T8

38

T16

4

auto[1]

auto[0]

auto[0]

auto[0]

1087

1

T2

2

T8

4

T14

6

auto[1]

auto[0]

auto[1]

auto[0]

5234

1

T1

7

T2

2

T4

3

auto[1]

auto[1]

auto[0]

auto[0]

1100

1

T8

8

T14

4

T23

8

auto[1]

auto[1]

auto[1]

auto[1]

5636

1

T1

1

T2

1

T4

4

User Defined Cross Bins for interrupt_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
no_wakeup	0	Excluded
disable_pin	0	Excluded
no_status_pin	0	Excluded
missing_int	0	Excluded