Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	548095	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

214844

1

T1

51

T2

63

T4

47

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	410176	1			T1	123		T2	131		T3	1
values[0x0]	176245	1			T1	45		T2	52		T4	64
values[0x1]	176518	1			T1	57		T2	67		T4	48

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	433547	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

329392

1

T1

84

T2

100

T4

78

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3348	1			T4	1		T8	22		T16	2
valid_sources[0x01]	2236	1			T1	1		T3	1		T4	3
valid_sources[0x02]	2198	1			T1	4		T8	21		T23	1
valid_sources[0x03]	2210	1			T1	1		T4	1		T7	1
valid_sources[0x04]	2314	1			T7	1		T8	20		T16	5
valid_sources[0x05]	3617	1			T2	5		T8	19		T10	1
valid_sources[0x06]	2655	1			T4	5		T5	2		T8	11
valid_sources[0x07]	2561	1			T4	2		T6	1		T8	31
valid_sources[0x08]	3805	1			T6	1		T8	21		T16	3
valid_sources[0x09]	2709	1			T1	2		T8	26		T10	1
valid_sources[0x0a]	2479	1			T1	2		T4	1		T7	2
valid_sources[0x0b]	4762	1			T1	1		T8	24		T23	8
valid_sources[0x0c]	2495	1			T1	1		T7	1		T8	14
valid_sources[0x0d]	2432	1			T4	1		T8	20		T23	3
valid_sources[0x0e]	4417	1			T1	2		T7	1		T8	20
valid_sources[0x0f]	2187	1			T4	1		T7	1		T8	23
valid_sources[0x10]	2662	1			T8	28		T16	2		T182	3
valid_sources[0x11]	2794	1			T1	1		T6	1		T8	19
valid_sources[0x12]	2896	1			T1	1		T2	1		T8	24
valid_sources[0x13]	2466	1			T4	1		T8	21		T14	2
valid_sources[0x14]	6092	1			T1	1		T2	6		T8	27
valid_sources[0x15]	4096	1			T4	1		T8	20		T16	5
valid_sources[0x16]	2170	1			T1	1		T7	1		T8	18
valid_sources[0x17]	2055	1			T7	1		T8	20		T16	4
valid_sources[0x18]	4980	1			T1	1		T7	1		T8	16
valid_sources[0x19]	2452	1			T1	1		T4	2		T7	2
valid_sources[0x1a]	3462	1			T2	1		T8	18		T16	4
valid_sources[0x1b]	3274	1			T2	8		T4	4		T8	17
valid_sources[0x1c]	2509	1			T8	28		T23	1		T16	3
valid_sources[0x1d]	2941	1			T4	4		T7	2		T8	15
valid_sources[0x1e]	2400	1			T1	2		T4	2		T7	7
valid_sources[0x1f]	2318	1			T1	1		T8	26		T16	11
valid_sources[0x20]	2384	1			T2	1		T8	18		T23	5
valid_sources[0x21]	2360	1			T1	2		T2	1		T4	1
valid_sources[0x22]	4197	1			T1	1		T2	13		T4	2
valid_sources[0x23]	2427	1			T4	5		T8	14		T16	3
valid_sources[0x24]	4622	1			T1	2		T4	4		T8	14
valid_sources[0x25]	2626	1			T1	3		T2	8		T4	4
valid_sources[0x26]	2623	1			T4	1		T8	17		T16	5
valid_sources[0x27]	2554	1			T6	1		T8	18		T23	22
valid_sources[0x28]	2718	1			T1	4		T4	3		T6	1
valid_sources[0x29]	2306	1			T1	1		T2	7		T4	1
valid_sources[0x2a]	2278	1			T4	1		T6	1		T8	21
valid_sources[0x2b]	3827	1			T4	1		T7	1		T8	23
valid_sources[0x2c]	3536	1			T8	30		T16	6		T36	2
valid_sources[0x2d]	2194	1			T6	1		T7	1		T8	20
valid_sources[0x2e]	2939	1			T8	16		T23	14		T16	4
valid_sources[0x2f]	2860	1			T4	1		T8	26		T23	4
valid_sources[0x30]	2610	1			T1	1		T8	17		T10	1
valid_sources[0x31]	2211	1			T1	4		T7	3		T8	17
valid_sources[0x32]	5053	1			T1	1		T8	19		T23	6
valid_sources[0x33]	2320	1			T4	8		T7	1		T8	20
valid_sources[0x34]	4814	1			T1	3		T2	17		T5	3
valid_sources[0x35]	3212	1			T1	1		T4	2		T8	23
valid_sources[0x36]	3835	1			T1	1		T2	1		T4	3
valid_sources[0x37]	2547	1			T1	1		T8	19		T23	1
valid_sources[0x38]	3996	1			T1	2		T4	2		T8	25
valid_sources[0x39]	2610	1			T1	4		T8	18		T16	3
valid_sources[0x3a]	3352	1			T4	2		T8	24		T14	52
valid_sources[0x3b]	2475	1			T8	16		T16	1		T37	33
valid_sources[0x3c]	2215	1			T1	1		T4	2		T7	1
valid_sources[0x3d]	5949	1			T1	1		T8	20		T16	10
valid_sources[0x3e]	2330	1			T1	1		T8	19		T16	3
valid_sources[0x3f]	2308	1			T4	2		T8	20		T23	10
valid_sources[0x40]	3109	1			T1	3		T2	4		T6	1
valid_sources[0x41]	2680	1			T4	1		T7	1		T8	21
valid_sources[0x42]	4139	1			T4	1		T8	17		T23	1
valid_sources[0x43]	3600	1			T4	1		T8	11		T23	2
valid_sources[0x44]	2310	1			T1	2		T2	5		T8	24
valid_sources[0x45]	2382	1			T1	1		T8	23		T16	6
valid_sources[0x46]	2369	1			T1	1		T4	1		T5	8
valid_sources[0x47]	4189	1			T1	1		T4	1		T8	27
valid_sources[0x48]	2602	1			T2	7		T6	1		T8	23
valid_sources[0x49]	2869	1			T8	18		T23	6		T16	4
valid_sources[0x4a]	2817	1			T1	1		T7	1		T8	14
valid_sources[0x4b]	2451	1			T4	5		T8	27		T23	4
valid_sources[0x4c]	2750	1			T1	3		T4	2		T7	1
valid_sources[0x4d]	2440	1			T1	2		T2	1		T7	1
valid_sources[0x4e]	2135	1			T7	1		T8	20		T16	4
valid_sources[0x4f]	3143	1			T8	18		T10	1		T16	5
valid_sources[0x50]	2687	1			T1	1		T4	1		T8	16
valid_sources[0x51]	2301	1			T1	7		T8	18		T23	12
valid_sources[0x52]	2300	1			T4	1		T8	17		T14	33
valid_sources[0x53]	3191	1			T1	3		T6	1		T8	29
valid_sources[0x54]	4118	1			T1	2		T7	1		T8	24
valid_sources[0x55]	2672	1			T1	1		T8	18		T16	5
valid_sources[0x56]	2523	1			T8	21		T16	4		T42	4
valid_sources[0x57]	3290	1			T1	1		T4	1		T8	21
valid_sources[0x58]	2356	1			T1	2		T4	1		T8	27
valid_sources[0x59]	4177	1			T8	21		T16	3		T42	8
valid_sources[0x5a]	2798	1			T4	1		T6	1		T8	21
valid_sources[0x5b]	3072	1			T4	5		T8	19		T10	2
valid_sources[0x5c]	2496	1			T1	1		T8	20		T14	8
valid_sources[0x5d]	2582	1			T1	2		T8	14		T16	6
valid_sources[0x5e]	4014	1			T4	1		T8	34		T14	54
valid_sources[0x5f]	4370	1			T8	16		T16	2		T42	1
valid_sources[0x60]	2695	1			T1	3		T7	2		T8	23
valid_sources[0x61]	2388	1			T1	1		T6	1		T8	22
valid_sources[0x62]	3008	1			T1	2		T2	10		T4	3
valid_sources[0x63]	3883	1			T1	2		T8	19		T16	7
valid_sources[0x64]	2636	1			T8	17		T10	1		T23	4
valid_sources[0x65]	3486	1			T4	3		T6	1		T8	21
valid_sources[0x66]	3476	1			T1	3		T4	2		T8	19
valid_sources[0x67]	4555	1			T1	2		T8	26		T16	4
valid_sources[0x68]	5599	1			T1	1		T4	5		T8	23
valid_sources[0x69]	2382	1			T4	4		T6	1		T8	11
valid_sources[0x6a]	5358	1			T4	1		T8	25		T23	10
valid_sources[0x6b]	2998	1			T1	3		T8	17		T16	9
valid_sources[0x6c]	2435	1			T4	2		T8	12		T16	4
valid_sources[0x6d]	2371	1			T1	3		T4	1		T7	1
valid_sources[0x6e]	3712	1			T8	22		T23	4		T16	2
valid_sources[0x6f]	2456	1			T1	1		T2	1		T7	1
valid_sources[0x70]	2278	1			T1	2		T8	20		T16	6
valid_sources[0x71]	3456	1			T4	2		T8	20		T23	3
valid_sources[0x72]	2484	1			T1	2		T8	24		T16	6
valid_sources[0x73]	2265	1			T7	1		T8	19		T23	19
valid_sources[0x74]	2278	1			T4	5		T8	9		T23	10
valid_sources[0x75]	2852	1			T1	1		T4	1		T8	20
valid_sources[0x76]	2473	1			T1	3		T7	1		T8	18
valid_sources[0x77]	5245	1			T1	4		T4	8		T8	27
valid_sources[0x78]	4565	1			T6	1		T8	18		T14	33
valid_sources[0x79]	2291	1			T2	3		T5	10		T8	31
valid_sources[0x7a]	2453	1			T7	1		T8	32		T23	12
valid_sources[0x7b]	2574	1			T2	8		T7	3		T8	24
valid_sources[0x7c]	2708	1			T2	4		T4	1		T7	1
valid_sources[0x7d]	3466	1			T1	2		T4	1		T8	18
valid_sources[0x7e]	2421	1			T4	1		T7	2		T8	29
valid_sources[0x7f]	2136	1			T1	2		T7	2		T8	16
valid_sources[0x80]	3340	1			T2	4		T8	29		T16	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

113797

1

T1

29

T2

33

T4

23

values[0x0]

all_enables

biggest_size

65563

1

T1

15

T2

18

T4

15

values[0x1]

all_enables

biggest_size

35484

1

T1

7

T2

12

T4

9