SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35009 | 1 | T23 | 305 | T15 | 1 | T178 | 288 | ||||
others[1] | 35067 | 1 | T23 | 299 | T178 | 294 | T195 | 387 | ||||
others[2] | 34892 | 1 | T23 | 268 | T178 | 301 | T195 | 396 | ||||
others[3] | 58382 | 1 | T23 | 506 | T178 | 510 | T195 | 673 | ||||
false | 19478 | 1 | T2 | 26 | T8 | 126 | T14 | 76 | ||||
true | 29940 | 1 | T1 | 1 | T2 | 27 | T3 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34844 | 1 | T23 | 275 | T15 | 1 | T51 | 1 | ||||
others[1] | 34876 | 1 | T23 | 319 | T24 | 1 | T178 | 303 | ||||
others[2] | 35021 | 1 | T23 | 282 | T178 | 297 | T195 | 399 | ||||
others[3] | 58656 | 1 | T23 | 512 | T178 | 516 | T195 | 683 | ||||
false | 12329 | 1 | T2 | 13 | T8 | 63 | T14 | 38 | ||||
true | 22848 | 1 | T1 | 1 | T2 | 14 | T3 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 734 | 1 | T8 | 6 | T14 | 1 | T182 | 3 | ||||
others[1] | 727 | 1 | T8 | 6 | T14 | 4 | T15 | 1 | ||||
others[2] | 685 | 1 | T8 | 10 | T14 | 1 | T182 | 6 | ||||
others[3] | 1162 | 1 | T8 | 7 | T14 | 1 | T15 | 1 | ||||
false | 14587 | 1 | T1 | 1 | T2 | 1 | T3 | 6 | ||||
true | 4438 | 1 | T8 | 52 | T14 | 20 | T15 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |