Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25801616	15277	0	0
intr_enable_rd_A	25801616	30504	0	0
reset_en_rd_A	25801616	1075	0	0
reset_en_regwen_rd_A	25801616	976	0	0
wake_info_capture_dis_rd_A	25801616	1025	0	0
wakeup_en_rd_A	25801616	1574	0	0
wakeup_en_regwen_rd_A	25801616	952	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25801616	15277	0	0
T8	139872	3	0	0
T9	2195	0	0	0
T10	1986	0	0	0
T14	49658	0	0	0
T15	5632	0	0	0
T16	36454	0	0	0
T17	1665	0	0	0
T21	0	13	0	0
T22	0	10	0	0
T23	32007	0	0	0
T41	1520	0	0	0
T42	16661	0	0	0
T55	0	12	0	0
T77	0	18	0	0
T84	0	10	0	0
T90	0	48	0	0
T147	0	10	0	0
T148	0	45	0	0
T149	0	35	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25801616	30504	0	0
T7	2158	33	0	0
T8	139872	0	0	0
T9	2195	0	0	0
T10	1986	0	0	0
T14	49658	214	0	0
T15	5632	26	0	0
T16	36454	0	0	0
T17	1665	0	0	0
T21	0	1858	0	0
T23	32007	87	0	0
T38	0	51	0	0
T41	1520	0	0	0
T45	0	133	0	0
T83	0	32	0	0
T150	0	33	0	0
T151	0	64	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25801616	1075	0	0
T11	635	0	0	0
T12	1371	0	0	0
T21	398879	13	0	0
T24	1813	0	0	0
T39	2396	0	0	0
T40	4107	0	0	0
T53	0	16	0	0
T54	0	83	0	0
T116	1651	0	0	0
T117	2897	0	0	0
T152	0	15	0	0
T153	0	22	0	0
T154	0	6	0	0
T155	0	7	0	0
T156	0	5	0	0
T157	0	9	0	0
T158	0	53	0	0
T159	3478	0	0	0
T160	1397	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25801616	976	0	0
T11	635	0	0	0
T12	1371	0	0	0
T21	398879	15	0	0
T24	1813	0	0	0
T39	2396	0	0	0
T40	4107	0	0	0
T53	0	10	0	0
T54	0	68	0	0
T66	0	97	0	0
T116	1651	0	0	0
T117	2897	0	0	0
T127	0	6	0	0
T153	0	15	0	0
T155	0	3	0	0
T156	0	7	0	0
T157	0	7	0	0
T158	0	61	0	0
T159	3478	0	0	0
T160	1397	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25801616	1025	0	0
T11	635	0	0	0
T12	1371	0	0	0
T21	398879	6	0	0
T24	1813	0	0	0
T39	2396	0	0	0
T40	4107	0	0	0
T53	0	28	0	0
T54	0	48	0	0
T116	1651	0	0	0
T117	2897	0	0	0
T152	0	6	0	0
T153	0	8	0	0
T154	0	10	0	0
T155	0	15	0	0
T156	0	6	0	0
T157	0	9	0	0
T158	0	48	0	0
T159	3478	0	0	0
T160	1397	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25801616	1574	0	0
T11	635	0	0	0
T12	1371	0	0	0
T21	398879	14	0	0
T24	1813	0	0	0
T39	2396	0	0	0
T40	4107	0	0	0
T53	0	29	0	0
T54	0	170	0	0
T116	1651	0	0	0
T117	2897	0	0	0
T152	0	5	0	0
T153	0	14	0	0
T154	0	7	0	0
T156	0	7	0	0
T157	0	10	0	0
T158	0	39	0	0
T159	3478	0	0	0
T160	1397	0	0	0
T161	0	6	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25801616	952	0	0
T53	0	14	0	0
T54	0	56	0	0
T66	0	65	0	0
T152	444806	1	0	0
T153	0	20	0	0
T154	0	12	0	0
T155	0	8	0	0
T156	0	13	0	0
T157	0	12	0	0
T158	0	68	0	0
T162	1175	0	0	0
T163	26124	0	0	0
T164	1445	0	0	0
T165	3147	0	0	0
T166	34068	0	0	0
T167	7731	0	0	0
T168	1255	0	0	0
T169	778	0	0	0
T170	21609	0	0	0