Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	75630318	152934	0	0
StatusRise_A	75630318	170873	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75630318	152934	0	0
T1	29499	41	0	0
T2	41073	59	0	0
T3	10941	0	0	0
T4	45618	41	0	0
T5	4830	6	0	0
T6	3939	6	0	0
T7	6474	34	0	0
T8	419616	1206	0	0
T9	6585	0	0	0
T10	5958	12	0	0
T14	0	391	0	0
T23	0	215	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75630318	170873	0	0
T1	29499	43	0	0
T2	41073	62	0	0
T3	10941	18	0	0
T4	45618	43	0	0
T5	4830	9	0	0
T6	3939	9	0	0
T7	6474	36	0	0
T8	419616	1367	0	0
T9	6585	9	0	0
T10	5958	15	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25210106	56696	0	0
StatusRise_A	25210106	63170	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25210106	56696	0	0
T1	9833	15	0	0
T2	13691	23	0	0
T3	3647	0	0	0
T4	15206	16	0	0
T5	1610	2	0	0
T6	1313	2	0	0
T7	2158	12	0	0
T8	139872	447	0	0
T9	2195	0	0	0
T10	1986	4	0	0
T14	0	148	0	0
T23	0	84	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25210106	63170	0	0
T1	9833	16	0	0
T2	13691	24	0	0
T3	3647	6	0	0
T4	15206	17	0	0
T5	1610	3	0	0
T6	1313	3	0	0
T7	2158	13	0	0
T8	139872	505	0	0
T9	2195	3	0	0
T10	1986	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25210106	56696	0	0
StatusRise_A	25210106	63171	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25210106	56696	0	0
T1	9833	15	0	0
T2	13691	23	0	0
T3	3647	0	0	0
T4	15206	16	0	0
T5	1610	2	0	0
T6	1313	2	0	0
T7	2158	12	0	0
T8	139872	447	0	0
T9	2195	0	0	0
T10	1986	4	0	0
T14	0	148	0	0
T23	0	84	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25210106	63171	0	0
T1	9833	16	0	0
T2	13691	24	0	0
T3	3647	6	0	0
T4	15206	17	0	0
T5	1610	3	0	0
T6	1313	3	0	0
T7	2158	13	0	0
T8	139872	505	0	0
T9	2195	3	0	0
T10	1986	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25210106	39542	0	0
StatusRise_A	25210106	44532	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25210106	39542	0	0
T1	9833	11	0	0
T2	13691	13	0	0
T3	3647	0	0	0
T4	15206	9	0	0
T5	1610	2	0	0
T6	1313	2	0	0
T7	2158	10	0	0
T8	139872	312	0	0
T9	2195	0	0	0
T10	1986	4	0	0
T14	0	95	0	0
T23	0	47	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25210106	44532	0	0
T1	9833	11	0	0
T2	13691	14	0	0
T3	3647	6	0	0
T4	15206	9	0	0
T5	1610	3	0	0
T6	1313	3	0	0
T7	2158	10	0	0
T8	139872	357	0	0
T9	2195	3	0	0
T10	1986	5	0	0