Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	25210676	4559	0	0
EscTimeoutStoppedByClReset_A	25210106	3656804	0	0
EscTimeoutTriggersReset_A	5181460	330	0	0
RomAllowActiveState_A	25210106	62779	0	0
RomAllowCheckGoodState_A	25210106	62829	0	0
RomBlockActiveState_A	25210106	28786	0	0
RomBlockCheckGoodState_A	25210106	410900	0	0
RomIntgChkDisFalse_A	25210106	24530604	0	0
RomIntgChkDisTrue_A	25210106	124587	0	0
RstreqChkEsctimeout_A	25210106	4736	0	0
RstreqChkFsmterm_A	25210106	180	0	0
RstreqChkGlbesc_A	25210106	4736	0	0
RstreqChkMainpd_A	25210106	1012292	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25210676	4559	0	0
T11	635	1	0	0
T12	1371	8	0	0
T13	0	130	0	0
T40	4108	0	0	0
T46	6096	0	0	0
T62	14297	0	0	0
T63	2802	0	0	0
T100	0	23	0	0
T116	1652	0	0	0
T117	2898	0	0	0
T159	3479	0	0	0
T160	1398	0	0	0
T171	0	32	0	0
T172	0	144	0	0
T173	0	30	0	0
T174	0	182	0	0
T175	0	116	0	0
T176	0	7	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25210106	3656804	0	0
T1	9833	1514	0	0
T2	13691	2441	0	0
T3	3647	80	0	0
T4	15206	3138	0	0
T5	1610	18	0	0
T6	1313	25	0	0
T7	2158	16	0	0
T8	139872	15052	0	0
T9	2195	42	0	0
T10	1986	37	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5181460	330	0	0
T11	378	7	0	0
T12	229	3	0	0
T13	0	2	0	0
T40	616	0	0	0
T46	646	0	0	0
T62	1582	0	0	0
T63	2223	0	0	0
T100	0	2	0	0
T116	324	0	0	0
T117	233	0	0	0
T159	997	0	0	0
T160	468	0	0	0
T171	0	3	0	0
T172	0	2	0	0
T173	0	2	0	0
T174	0	2	0	0
T175	0	2	0	0
T177	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25210106	62779	0	0
T1	9833	16	0	0
T2	13691	24	0	0
T3	3647	6	0	0
T4	15206	17	0	0
T5	1610	3	0	0
T6	1313	3	0	0
T7	2158	13	0	0
T8	139872	505	0	0
T9	2195	3	0	0
T10	1986	5	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25210106	62829	0	0
T1	9833	16	0	0
T2	13691	24	0	0
T3	3647	6	0	0
T4	15206	17	0	0
T5	1610	3	0	0
T6	1313	3	0	0
T7	2158	13	0	0
T8	139872	505	0	0
T9	2195	3	0	0
T10	1986	5	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25210106	28786	0	0
T15	5632	901	0	0
T16	36454	0	0	0
T17	1665	0	0	0
T24	0	283	0	0
T36	27691	0	0	0
T41	1520	0	0	0
T42	16661	0	0	0
T43	1906	0	0	0
T45	15329	0	0	0
T51	0	1410	0	0
T83	1680	0	0	0
T92	0	2	0	0
T93	0	1522	0	0
T104	0	300	0	0
T178	0	12	0	0
T179	0	1012	0	0
T180	0	30	0	0
T181	0	16	0	0
T182	6240	0	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25210106	410900	0	0
T2	13691	297	0	0
T3	3647	0	0	0
T4	15206	0	0	0
T5	1610	0	0	0
T6	1313	0	0	0
T7	2158	0	0	0
T8	139872	1446	0	0
T9	2195	0	0	0
T10	1986	0	0	0
T14	49658	868	0	0
T15	0	838	0	0
T16	0	69	0	0
T21	0	2271	0	0
T23	0	1993	0	0
T24	0	95	0	0
T37	0	92	0	0
T38	0	322	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25210106	24530604	0	0
T1	9833	9753	0	0
T2	13691	13599	0	0
T3	3647	3249	0	0
T4	15206	15151	0	0
T5	1610	1553	0	0
T6	1313	1235	0	0
T7	2158	2108	0	0
T8	139872	135674	0	0
T9	2195	1985	0	0
T10	1986	1539	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25210106	124587	0	0
T15	5632	480	0	0
T16	36454	0	0	0
T17	1665	0	0	0
T23	32007	721	0	0
T24	0	829	0	0
T41	1520	0	0	0
T42	16661	0	0	0
T43	1906	0	0	0
T45	15329	0	0	0
T51	0	672	0	0
T83	1680	0	0	0
T93	0	188	0	0
T104	0	70	0	0
T178	0	246	0	0
T179	0	1588	0	0
T182	6240	0	0	0
T183	0	953	0	0
T184	0	1243	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25210106	4736	0	0
T8	139872	51	0	0
T9	2195	0	0	0
T10	1986	0	0	0
T14	49658	17	0	0
T15	5632	5	0	0
T16	36454	0	0	0
T17	1665	0	0	0
T21	0	19	0	0
T23	32007	0	0	0
T24	0	3	0	0
T36	0	8	0	0
T37	0	6	0	0
T39	0	10	0	0
T41	1520	0	0	0
T42	16661	0	0	0
T43	0	4	0	0
T44	0	2	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25210106	180	0	0
T18	10806	20	0	0
T19	0	40	0	0
T20	0	40	0	0
T25	0	40	0	0
T26	0	40	0	0
T27	1542	0	0	0
T28	20582	0	0	0
T29	5342	0	0	0
T30	48510	0	0	0
T31	802	0	0	0
T32	16936	0	0	0
T33	84065	0	0	0
T34	3628	0	0	0
T35	3604	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25210106	4736	0	0
T8	139872	51	0	0
T9	2195	0	0	0
T10	1986	0	0	0
T14	49658	17	0	0
T15	5632	5	0	0
T16	36454	0	0	0
T17	1665	0	0	0
T21	0	19	0	0
T23	32007	0	0	0
T24	0	3	0	0
T36	0	8	0	0
T37	0	6	0	0
T39	0	10	0	0
T41	1520	0	0	0
T42	16661	0	0	0
T43	0	4	0	0
T44	0	2	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25210106	1012292	0	0
T2	13691	1983	0	0
T3	3647	23	0	0
T4	15206	0	0	0
T5	1610	0	0	0
T6	1313	0	0	0
T7	2158	0	0	0
T8	139872	2974	0	0
T9	2195	11	0	0
T10	1986	0	0	0
T14	49658	2596	0	0
T15	0	776	0	0
T17	0	11	0	0
T23	0	2676	0	0
T36	0	646	0	0
T37	0	1124	0	0