Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33399

1

T2

8

T3

3

T7

20

auto[1]

32454

1

T2

12

T3

3

T7

10

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33800

1

T2

8

T7

8

T8

2

auto[1]

32053

1

T2

12

T3

6

T7

22

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32262

1

T2

6

T3

6

T7

14

auto[1]

33591

1

T2

14

T7

16

T8

2

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36930

1

T2

10

T3

4

T7

15

auto[1]

28923

1

T2

10

T3

2

T7

15

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32315

1

T2

12

T3

1

T7

24

auto[1]

33538

1

T2

8

T3

5

T7

6

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33682

1

T2

10

T3

1

T7

10

auto[1]

32171

1

T2

10

T3

5

T7

20

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1139

1

T7

1

T9

11

T38

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

887

1

T7

1

T9

7

T38

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1113

1

T9

11

T38

1

T58

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

846

1

T9

9

T38

1

T58

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1123

1

T9

8

T24

3

T15

15

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

880

1

T9

6

T24

3

T15

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1891

1

T2

1

T8

1

T9

26

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1633

1

T2

1

T8

1

T9

26

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1137

1

T7

1

T9

10

T44

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

876

1

T7

1

T9

7

T44

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1128

1

T2

1

T7

2

T9

9

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

893

1

T2

1

T7

2

T9

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1197

1

T9

13

T38

2

T54

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

931

1

T9

10

T38

2

T54

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1075

1

T2

1

T9

9

T39

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

854

1

T2

1

T9

6

T39

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1057

1

T2

1

T7

1

T9

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

843

1

T2

1

T7

1

T9

9

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1194

1

T7

1

T9

8

T38

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

937

1

T7

1

T9

7

T38

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1091

1

T9

12

T39

1

T54

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

849

1

T9

8

T39

1

T54

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1085

1

T7

1

T9

9

T38

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

830

1

T7

1

T9

7

T38

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1127

1

T3

1

T9

11

T39

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

878

1

T9

7

T39

2

T15

13

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1151

1

T7

2

T9

12

T38

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

899

1

T7

2

T9

10

T38

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1102

1

T3

1

T9

10

T38

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

863

1

T3

1

T9

9

T38

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1065

1

T7

1

T9

10

T38

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

825

1

T7

1

T9

7

T38

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1129

1

T9

13

T38

1

T54

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

882

1

T9

11

T38

1

T54

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1189

1

T9

13

T44

1

T38

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

921

1

T9

8

T38

1

T39

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1133

1

T9

7

T44

1

T38

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

910

1

T9

5

T38

2

T39

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1077

1

T9

9

T38

2

T39

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

866

1

T9

8

T38

2

T39

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1104

1

T2

1

T9

9

T38

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

856

1

T2

1

T9

6

T38

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1160

1

T9

8

T38

1

T24

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

915

1

T9

6

T38

1

T24

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1163

1

T9

13

T38

2

T39

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

885

1

T9

11

T38

2

T39

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1118

1

T9

17

T58

1

T24

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

889

1

T9

16

T58

1

T24

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1122

1

T9

8

T38

1

T58

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

883

1

T9

7

T38

1

T58

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1133

1

T2

2

T9

8

T38

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

875

1

T2

2

T9

7

T38

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1165

1

T3

1

T7

1

T9

7

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

913

1

T7

1

T9

5

T38

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1183

1

T2

1

T9

4

T38

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

903

1

T2

1

T9

2

T38

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1179

1

T7

3

T9

8

T24

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

906

1

T7

3

T9

6

T24

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1116

1

T2

1

T7

1

T9

11

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

840

1

T2

1

T7

1

T9

9

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1159

1

T2

1

T3

1

T9

13

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

893

1

T2

1

T3

1

T9

10

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1125

1

T9

11

T39

1

T54

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

862

1

T9

7

T39

1

T54

2