Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
debug_cp	2	0	2	100.00	100	1	1	0
dft_cp	2	0	2	100.00	100	1	1	0
done_cp	2	0	2	100.00	100	1	1	0
good_cp	2	0	2	100.00	100	1	1	0

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
blockers_cross	16	1	15	93.75	100	1	1	0

Summary for Variable debug_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for debug_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	48741	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

off

170597

1

T1

13

T2

1

T3

1

on

17984

1

T1

1

T10

3

T24

189

---

Summary for Variable dft_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for dft_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40456	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

off

172338

1

T1

8

T2

1

T3

1

on

24528

1

T1

3

T10

10

T24

914

---

Summary for Variable done_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for done_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	182959	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

34894

1

T1

5

T7

60

T9

557

true

19469

1

T1

9

T2

1

T3

1

---

Summary for Variable good_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for good_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	175479	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

20263

1

T1

7

T7

30

T9

281

true

41580

1

T1

7

T2

1

T3

1

---

Summary for Cross blockers_cross

Samples crossed: done_cp good_cp dft_cp debug_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for blockers_cross

Uncovered bins

done_cp	good_cp	dft_cp	debug_cp	COUNT	AT LEAST	NUMBER	STATUS
[false]	[true]	[on]	[on]	0	1	1

Covered bins

done_cp

good_cp

dft_cp

debug_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

false

off

off

17471

1

T1

2

T7

30

T9

278

false

false

off

on

154

1

T46

1

T182

1

T179

1

false

false

on

off

165

1

T24

5

T179

1

T104

1

false

false

on

on

210

1

T24

3

T182

1

T179

1

false

true

off

off

14835

1

T1

1

T7

30

T9

276

false

true

off

on

3

1

T181

2

T188

1

-

-

false

true

on

off

3

1

T1

1

T189

1

T190

1

true

false

off

off

53

1

T1

2

T46

1

T149

3

true

false

off

on

15

1

T46

1

T179

1

T191

1

true

false

on

off

20

1

T179

1

T189

1

T192

1

true

false

on

on

88

1

T1

1

T46

2

T149

2

true

true

off

off

13851

1

T1

3

T2

1

T3

1

true

true

off

on

346

1

T24

3

T46

1

T182

4

true

true

on

off

317

1

T1

1

T24

4

T182

3

true

true

on

on

357

1

T24

5

T182

5

T104

8