Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7707 |
1 |
|
|
T5 |
11 |
|
T7 |
11 |
|
T9 |
69 |
auto[1] |
20855 |
1 |
|
|
T2 |
5 |
|
T5 |
41 |
|
T6 |
1 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12911 |
1 |
|
|
T2 |
3 |
|
T5 |
29 |
|
T7 |
8 |
auto[1] |
15651 |
1 |
|
|
T2 |
2 |
|
T5 |
23 |
|
T6 |
1 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13612 |
1 |
|
|
T2 |
3 |
|
T5 |
29 |
|
T7 |
9 |
auto[1] |
14950 |
1 |
|
|
T2 |
2 |
|
T5 |
23 |
|
T6 |
1 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1735 |
1 |
|
|
T5 |
3 |
|
T7 |
4 |
|
T9 |
13 |
auto[0] |
auto[0] |
auto[1] |
1835 |
1 |
|
|
T5 |
2 |
|
T7 |
1 |
|
T9 |
15 |
auto[0] |
auto[1] |
auto[0] |
4899 |
1 |
|
|
T2 |
2 |
|
T5 |
15 |
|
T7 |
1 |
auto[0] |
auto[1] |
auto[1] |
4442 |
1 |
|
|
T2 |
1 |
|
T5 |
9 |
|
T7 |
2 |
auto[1] |
auto[0] |
auto[0] |
1809 |
1 |
|
|
T5 |
3 |
|
T7 |
2 |
|
T9 |
20 |
auto[1] |
auto[0] |
auto[1] |
2328 |
1 |
|
|
T5 |
3 |
|
T7 |
4 |
|
T9 |
21 |
auto[1] |
auto[1] |
auto[0] |
5169 |
1 |
|
|
T2 |
1 |
|
T5 |
8 |
|
T7 |
2 |
auto[1] |
auto[1] |
auto[1] |
6345 |
1 |
|
|
T2 |
1 |
|
T5 |
9 |
|
T6 |
1 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7707 |
1 |
|
|
T5 |
11 |
|
T7 |
11 |
|
T9 |
69 |
auto[1] |
20855 |
1 |
|
|
T2 |
5 |
|
T5 |
41 |
|
T6 |
1 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13020 |
1 |
|
|
T2 |
1 |
|
T5 |
31 |
|
T7 |
10 |
auto[1] |
15542 |
1 |
|
|
T2 |
4 |
|
T5 |
21 |
|
T6 |
1 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13604 |
1 |
|
|
T5 |
23 |
|
T6 |
1 |
|
T7 |
7 |
auto[1] |
14958 |
1 |
|
|
T2 |
5 |
|
T5 |
29 |
|
T7 |
13 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1797 |
1 |
|
|
T5 |
4 |
|
T7 |
2 |
|
T9 |
15 |
auto[0] |
auto[0] |
auto[1] |
1791 |
1 |
|
|
T5 |
3 |
|
T7 |
1 |
|
T9 |
19 |
auto[0] |
auto[1] |
auto[0] |
4953 |
1 |
|
|
T5 |
15 |
|
T7 |
2 |
|
T8 |
12 |
auto[0] |
auto[1] |
auto[1] |
4479 |
1 |
|
|
T2 |
1 |
|
T5 |
9 |
|
T7 |
5 |
auto[1] |
auto[0] |
auto[0] |
1731 |
1 |
|
|
T5 |
1 |
|
T7 |
1 |
|
T9 |
13 |
auto[1] |
auto[0] |
auto[1] |
2388 |
1 |
|
|
T5 |
3 |
|
T7 |
7 |
|
T9 |
22 |
auto[1] |
auto[1] |
auto[0] |
5123 |
1 |
|
|
T5 |
3 |
|
T6 |
1 |
|
T7 |
2 |
auto[1] |
auto[1] |
auto[1] |
6300 |
1 |
|
|
T2 |
4 |
|
T5 |
14 |
|
T8 |
17 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7707 |
1 |
|
|
T5 |
11 |
|
T7 |
11 |
|
T9 |
69 |
auto[1] |
20855 |
1 |
|
|
T2 |
5 |
|
T5 |
41 |
|
T6 |
1 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12897 |
1 |
|
|
T2 |
5 |
|
T5 |
20 |
|
T7 |
6 |
auto[1] |
15665 |
1 |
|
|
T5 |
32 |
|
T6 |
1 |
|
T7 |
14 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13702 |
1 |
|
|
T2 |
2 |
|
T5 |
21 |
|
T7 |
12 |
auto[1] |
14860 |
1 |
|
|
T2 |
3 |
|
T5 |
31 |
|
T6 |
1 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1799 |
1 |
|
|
T5 |
2 |
|
T7 |
3 |
|
T9 |
19 |
auto[0] |
auto[0] |
auto[1] |
1719 |
1 |
|
|
T5 |
6 |
|
T7 |
1 |
|
T9 |
19 |
auto[0] |
auto[1] |
auto[0] |
4971 |
1 |
|
|
T2 |
2 |
|
T5 |
5 |
|
T7 |
1 |
auto[0] |
auto[1] |
auto[1] |
4408 |
1 |
|
|
T2 |
3 |
|
T5 |
7 |
|
T7 |
1 |
auto[1] |
auto[0] |
auto[0] |
1806 |
1 |
|
|
T5 |
1 |
|
T7 |
5 |
|
T9 |
12 |
auto[1] |
auto[0] |
auto[1] |
2383 |
1 |
|
|
T5 |
2 |
|
T7 |
2 |
|
T9 |
19 |
auto[1] |
auto[1] |
auto[0] |
5126 |
1 |
|
|
T5 |
13 |
|
T7 |
3 |
|
T8 |
15 |
auto[1] |
auto[1] |
auto[1] |
6350 |
1 |
|
|
T5 |
16 |
|
T6 |
1 |
|
T7 |
4 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7707 |
1 |
|
|
T5 |
11 |
|
T7 |
11 |
|
T9 |
69 |
auto[1] |
20855 |
1 |
|
|
T2 |
5 |
|
T5 |
41 |
|
T6 |
1 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12849 |
1 |
|
|
T2 |
2 |
|
T5 |
19 |
|
T7 |
11 |
auto[1] |
15713 |
1 |
|
|
T2 |
3 |
|
T5 |
33 |
|
T6 |
1 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13630 |
1 |
|
|
T2 |
4 |
|
T5 |
26 |
|
T6 |
1 |
auto[1] |
14932 |
1 |
|
|
T2 |
1 |
|
T5 |
26 |
|
T7 |
15 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1759 |
1 |
|
|
T5 |
5 |
|
T7 |
3 |
|
T9 |
20 |
auto[0] |
auto[0] |
auto[1] |
1756 |
1 |
|
|
T7 |
2 |
|
T9 |
15 |
|
T13 |
16 |
auto[0] |
auto[1] |
auto[0] |
4937 |
1 |
|
|
T2 |
1 |
|
T5 |
8 |
|
T7 |
2 |
auto[0] |
auto[1] |
auto[1] |
4397 |
1 |
|
|
T2 |
1 |
|
T5 |
6 |
|
T7 |
4 |
auto[1] |
auto[0] |
auto[0] |
1787 |
1 |
|
|
T5 |
3 |
|
T9 |
13 |
|
T13 |
32 |
auto[1] |
auto[0] |
auto[1] |
2405 |
1 |
|
|
T5 |
3 |
|
T7 |
6 |
|
T9 |
21 |
auto[1] |
auto[1] |
auto[0] |
5147 |
1 |
|
|
T2 |
3 |
|
T5 |
10 |
|
T6 |
1 |
auto[1] |
auto[1] |
auto[1] |
6374 |
1 |
|
|
T5 |
17 |
|
T7 |
3 |
|
T8 |
17 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7707 |
1 |
|
|
T5 |
11 |
|
T7 |
11 |
|
T9 |
69 |
auto[1] |
20855 |
1 |
|
|
T2 |
5 |
|
T5 |
41 |
|
T6 |
1 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12954 |
1 |
|
|
T2 |
3 |
|
T5 |
28 |
|
T7 |
12 |
auto[1] |
15608 |
1 |
|
|
T2 |
2 |
|
T5 |
24 |
|
T6 |
1 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13575 |
1 |
|
|
T2 |
2 |
|
T5 |
24 |
|
T7 |
9 |
auto[1] |
14987 |
1 |
|
|
T2 |
3 |
|
T5 |
28 |
|
T6 |
1 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1785 |
1 |
|
|
T5 |
4 |
|
T7 |
3 |
|
T9 |
19 |
auto[0] |
auto[0] |
auto[1] |
1777 |
1 |
|
|
T5 |
2 |
|
T7 |
3 |
|
T9 |
12 |
auto[0] |
auto[1] |
auto[0] |
4904 |
1 |
|
|
T2 |
1 |
|
T5 |
8 |
|
T7 |
2 |
auto[0] |
auto[1] |
auto[1] |
4488 |
1 |
|
|
T2 |
2 |
|
T5 |
14 |
|
T7 |
4 |
auto[1] |
auto[0] |
auto[0] |
1719 |
1 |
|
|
T5 |
2 |
|
T7 |
3 |
|
T9 |
18 |
auto[1] |
auto[0] |
auto[1] |
2426 |
1 |
|
|
T5 |
3 |
|
T7 |
2 |
|
T9 |
20 |
auto[1] |
auto[1] |
auto[0] |
5167 |
1 |
|
|
T2 |
1 |
|
T5 |
10 |
|
T7 |
1 |
auto[1] |
auto[1] |
auto[1] |
6296 |
1 |
|
|
T2 |
1 |
|
T5 |
9 |
|
T6 |
1 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7707 |
1 |
|
|
T5 |
11 |
|
T7 |
11 |
|
T9 |
69 |
auto[1] |
20855 |
1 |
|
|
T2 |
5 |
|
T5 |
41 |
|
T6 |
1 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12911 |
1 |
|
|
T2 |
3 |
|
T5 |
21 |
|
T7 |
13 |
auto[1] |
15651 |
1 |
|
|
T2 |
2 |
|
T5 |
31 |
|
T6 |
1 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13460 |
1 |
|
|
T2 |
2 |
|
T5 |
23 |
|
T6 |
1 |
auto[1] |
15102 |
1 |
|
|
T2 |
3 |
|
T5 |
29 |
|
T7 |
10 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1782 |
1 |
|
|
T5 |
4 |
|
T7 |
4 |
|
T9 |
8 |
auto[0] |
auto[0] |
auto[1] |
1800 |
1 |
|
|
T5 |
2 |
|
T7 |
4 |
|
T9 |
24 |
auto[0] |
auto[1] |
auto[0] |
4797 |
1 |
|
|
T2 |
1 |
|
T5 |
7 |
|
T7 |
3 |
auto[0] |
auto[1] |
auto[1] |
4532 |
1 |
|
|
T2 |
2 |
|
T5 |
8 |
|
T7 |
2 |
auto[1] |
auto[0] |
auto[0] |
1749 |
1 |
|
|
T5 |
2 |
|
T7 |
2 |
|
T9 |
15 |
auto[1] |
auto[0] |
auto[1] |
2376 |
1 |
|
|
T5 |
3 |
|
T7 |
1 |
|
T9 |
22 |
auto[1] |
auto[1] |
auto[0] |
5132 |
1 |
|
|
T2 |
1 |
|
T5 |
10 |
|
T6 |
1 |
auto[1] |
auto[1] |
auto[1] |
6394 |
1 |
|
|
T2 |
1 |
|
T5 |
16 |
|
T7 |
3 |