Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	527184	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

201937

1

T2

23

T3

6

T4

28

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	381037	1			T1	1		T2	47		T3	21
values[0x0]	173621	1			T2	19		T3	5		T4	32
values[0x1]	174463	1			T2	28		T3	5		T4	30

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	417397	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

311724

1

T2

34

T3

12

T4

90

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2523	1			T4	1		T5	6		T7	1
valid_sources[0x01]	2117	1			T5	7		T7	6		T9	21
valid_sources[0x02]	3145	1			T4	8		T5	13		T6	1
valid_sources[0x03]	2322	1			T7	7		T8	13		T9	20
valid_sources[0x04]	4210	1			T4	2		T7	1		T8	19
valid_sources[0x05]	3144	1			T5	19		T6	2		T8	20
valid_sources[0x06]	3074	1			T9	21		T13	33		T21	4
valid_sources[0x07]	2241	1			T4	5		T5	7		T7	6
valid_sources[0x08]	2101	1			T8	4		T9	14		T13	27
valid_sources[0x09]	2191	1			T5	10		T9	20		T13	43
valid_sources[0x0a]	1891	1			T7	3		T8	4		T9	10
valid_sources[0x0b]	2556	1			T7	1		T8	15		T9	21
valid_sources[0x0c]	2206	1			T5	4		T7	10		T8	16
valid_sources[0x0d]	2424	1			T4	2		T9	15		T13	45
valid_sources[0x0e]	2352	1			T4	1		T5	4		T9	26
valid_sources[0x0f]	2210	1			T2	1		T6	1		T7	7
valid_sources[0x10]	2973	1			T9	13		T13	44		T21	3
valid_sources[0x11]	2067	1			T5	32		T8	8		T9	28
valid_sources[0x12]	4725	1			T4	3		T5	6		T7	1
valid_sources[0x13]	2024	1			T4	1		T7	4		T8	32
valid_sources[0x14]	2199	1			T3	1		T4	2		T5	5
valid_sources[0x15]	2861	1			T4	1		T5	51		T7	1
valid_sources[0x16]	2850	1			T5	6		T7	4		T8	10
valid_sources[0x17]	4138	1			T5	10		T8	3		T9	17
valid_sources[0x18]	2439	1			T7	1		T8	1		T9	21
valid_sources[0x19]	2208	1			T7	2		T8	1		T9	30
valid_sources[0x1a]	3328	1			T5	23		T7	2		T9	14
valid_sources[0x1b]	2904	1			T4	3		T6	1		T7	1
valid_sources[0x1c]	2141	1			T4	2		T5	5		T6	1
valid_sources[0x1d]	3751	1			T5	3		T7	1		T8	14
valid_sources[0x1e]	2057	1			T5	39		T8	3		T9	19
valid_sources[0x1f]	2099	1			T7	4		T8	4		T9	17
valid_sources[0x20]	2199	1			T4	6		T8	3		T9	21
valid_sources[0x21]	3044	1			T4	1		T5	5		T7	5
valid_sources[0x22]	2124	1			T5	37		T8	8		T9	17
valid_sources[0x23]	2116	1			T6	1		T8	20		T9	25
valid_sources[0x24]	6477	1			T4	1		T6	1		T7	1
valid_sources[0x25]	2625	1			T4	1		T5	10		T8	2
valid_sources[0x26]	2124	1			T5	7		T8	3		T9	19
valid_sources[0x27]	2522	1			T3	1		T5	5		T7	2
valid_sources[0x28]	2409	1			T5	19		T7	2		T8	5
valid_sources[0x29]	3430	1			T3	2		T4	3		T5	1
valid_sources[0x2a]	2190	1			T5	14		T7	1		T9	13
valid_sources[0x2b]	3188	1			T5	36		T8	28		T9	19
valid_sources[0x2c]	2230	1			T6	1		T8	6		T9	16
valid_sources[0x2d]	2336	1			T9	12		T13	50		T21	11
valid_sources[0x2e]	2595	1			T5	23		T9	22		T13	38
valid_sources[0x2f]	6264	1			T5	26		T6	1		T7	1
valid_sources[0x30]	4079	1			T2	8		T6	1		T7	1
valid_sources[0x31]	3505	1			T4	5		T5	55		T7	1
valid_sources[0x32]	3015	1			T5	57		T8	1		T9	12
valid_sources[0x33]	2080	1			T4	2		T5	10		T8	12
valid_sources[0x34]	3593	1			T4	5		T5	25		T9	24
valid_sources[0x35]	3644	1			T4	1		T5	6		T6	1
valid_sources[0x36]	4207	1			T4	2		T6	1		T9	24
valid_sources[0x37]	2810	1			T4	2		T5	14		T7	3
valid_sources[0x38]	2051	1			T9	19		T13	14		T21	2
valid_sources[0x39]	3421	1			T5	5		T9	13		T13	60
valid_sources[0x3a]	2142	1			T7	2		T8	5		T9	21
valid_sources[0x3b]	2399	1			T5	32		T7	1		T9	22
valid_sources[0x3c]	1876	1			T8	9		T9	14		T13	29
valid_sources[0x3d]	2173	1			T6	1		T7	3		T9	28
valid_sources[0x3e]	4393	1			T5	8		T7	5		T9	20
valid_sources[0x3f]	3173	1			T5	6		T8	5		T9	19
valid_sources[0x40]	2052	1			T4	2		T5	29		T7	3
valid_sources[0x41]	2839	1			T4	1		T6	1		T7	1
valid_sources[0x42]	2345	1			T4	4		T5	27		T6	1
valid_sources[0x43]	2355	1			T4	5		T7	2		T8	3
valid_sources[0x44]	2248	1			T5	31		T7	1		T8	5
valid_sources[0x45]	3529	1			T4	2		T5	3		T9	20
valid_sources[0x46]	2081	1			T5	1		T7	11		T9	10
valid_sources[0x47]	2381	1			T5	3		T8	6		T9	21
valid_sources[0x48]	3027	1			T2	1		T4	1		T5	17
valid_sources[0x49]	2811	1			T5	5		T6	1		T7	4
valid_sources[0x4a]	2585	1			T5	17		T8	2		T9	20
valid_sources[0x4b]	2345	1			T7	1		T8	11		T9	12
valid_sources[0x4c]	1948	1			T7	1		T8	4		T9	15
valid_sources[0x4d]	2179	1			T3	2		T4	4		T7	6
valid_sources[0x4e]	2471	1			T5	22		T8	1		T9	24
valid_sources[0x4f]	4138	1			T4	1		T5	14		T7	1
valid_sources[0x50]	2107	1			T4	5		T6	1		T7	1
valid_sources[0x51]	2842	1			T5	33		T6	2		T7	1
valid_sources[0x52]	4203	1			T3	1		T4	1		T5	11
valid_sources[0x53]	2106	1			T9	14		T13	27		T21	8
valid_sources[0x54]	2541	1			T5	3		T9	18		T13	16
valid_sources[0x55]	5551	1			T5	12		T7	2		T9	20
valid_sources[0x56]	4406	1			T4	1		T5	20		T7	4
valid_sources[0x57]	6967	1			T8	1		T9	21		T13	38
valid_sources[0x58]	2402	1			T4	3		T9	22		T13	42
valid_sources[0x59]	2614	1			T5	37		T8	21		T9	22
valid_sources[0x5a]	3016	1			T3	2		T5	2		T7	1
valid_sources[0x5b]	5144	1			T9	23		T13	37		T21	3
valid_sources[0x5c]	3066	1			T5	4		T7	2		T8	17
valid_sources[0x5d]	2270	1			T8	4		T9	22		T13	36
valid_sources[0x5e]	2082	1			T3	2		T5	3		T8	4
valid_sources[0x5f]	3880	1			T9	11		T13	28		T21	5
valid_sources[0x60]	2176	1			T9	21		T13	33		T21	5
valid_sources[0x61]	2240	1			T7	1		T9	22		T13	31
valid_sources[0x62]	3090	1			T9	18		T13	49		T21	2
valid_sources[0x63]	7869	1			T5	9		T7	1		T9	19
valid_sources[0x64]	2926	1			T3	1		T4	1		T8	1
valid_sources[0x65]	1973	1			T4	2		T5	12		T9	19
valid_sources[0x66]	2169	1			T5	30		T7	1		T9	18
valid_sources[0x67]	2977	1			T3	2		T5	1		T8	18
valid_sources[0x68]	3085	1			T4	3		T5	2		T9	15
valid_sources[0x69]	4221	1			T4	5		T6	1		T8	2
valid_sources[0x6a]	2121	1			T5	28		T7	2		T9	16
valid_sources[0x6b]	2484	1			T8	8		T9	22		T13	48
valid_sources[0x6c]	2460	1			T5	22		T7	6		T8	5
valid_sources[0x6d]	4165	1			T4	1		T7	2		T9	21
valid_sources[0x6e]	1994	1			T5	2		T6	2		T8	2
valid_sources[0x6f]	3606	1			T5	18		T7	1		T8	8
valid_sources[0x70]	2641	1			T5	13		T7	1		T8	4
valid_sources[0x71]	2370	1			T5	5		T7	2		T9	24
valid_sources[0x72]	2848	1			T9	23		T13	31		T21	4
valid_sources[0x73]	3229	1			T8	2		T9	25		T13	44
valid_sources[0x74]	3537	1			T8	6		T9	15		T13	43
valid_sources[0x75]	2027	1			T4	1		T5	6		T7	3
valid_sources[0x76]	2030	1			T4	6		T9	17		T13	53
valid_sources[0x77]	2202	1			T8	18		T9	22		T13	83
valid_sources[0x78]	2311	1			T4	1		T9	26		T13	46
valid_sources[0x79]	3030	1			T5	10		T9	25		T13	26
valid_sources[0x7a]	2064	1			T6	2		T7	4		T9	28
valid_sources[0x7b]	2963	1			T5	2		T9	19		T13	66
valid_sources[0x7c]	3766	1			T4	6		T9	15		T13	30
valid_sources[0x7d]	2480	1			T4	1		T5	5		T7	4
valid_sources[0x7e]	2280	1			T5	6		T9	19		T13	80
valid_sources[0x7f]	2236	1			T4	1		T5	26		T7	1
valid_sources[0x80]	2273	1			T4	4		T8	3		T9	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

101820

1

T2

13

T3

5

T4

15

values[0x0]

all_enables

biggest_size

64824

1

T2

7

T3

1

T4

8

values[0x1]

all_enables

biggest_size

35293

1

T2

3

T4

5

T5

85