Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	26106604	15866	0	0
intr_enable_rd_A	26106604	47527	0	0
reset_en_rd_A	26106604	1454	0	0
reset_en_regwen_rd_A	26106604	1202	0	0
wake_info_capture_dis_rd_A	26106604	1251	0	0
wakeup_en_rd_A	26106604	2268	0	0
wakeup_en_regwen_rd_A	26106604	1335	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26106604	15866	0	0
T9	291221	12	0	0
T10	797	0	0	0
T11	15868	0	0	0
T12	789	0	0	0
T13	355093	37	0	0
T20	0	6	0	0
T21	16926	0	0	0
T38	14943	0	0	0
T39	853	0	0	0
T50	0	123	0	0
T55	0	28	0	0
T80	10956	0	0	0
T85	3648	0	0	0
T86	0	17	0	0
T90	0	7	0	0
T124	0	3	0	0
T125	0	26	0	0
T126	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26106604	47527	0	0
T2	6056	12	0	0
T3	3034	0	0	0
T4	4820	0	0	0
T5	45335	0	0	0
T6	1551	0	0	0
T7	18503	0	0	0
T8	14230	0	0	0
T9	291221	779	0	0
T10	797	0	0	0
T11	15868	0	0	0
T30	0	48	0	0
T37	0	74	0	0
T46	0	8	0	0
T82	0	72	0	0
T85	0	111	0	0
T127	0	1	0	0
T128	0	21	0	0
T129	0	30	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26106604	1454	0	0
T9	291221	7	0	0
T10	797	0	0	0
T11	15868	0	0	0
T12	789	0	0	0
T13	355093	0	0	0
T21	16926	0	0	0
T38	14943	0	0	0
T39	853	0	0	0
T80	10956	0	0	0
T85	3648	0	0	0
T90	0	8	0	0
T124	0	8	0	0
T125	0	15	0	0
T130	0	9	0	0
T131	0	8	0	0
T132	0	15	0	0
T133	0	3	0	0
T134	0	9	0	0
T135	0	2	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26106604	1202	0	0
T90	0	4	0	0
T92	0	18	0	0
T99	97316	0	0	0
T125	962283	3	0	0
T130	0	6	0	0
T131	0	10	0	0
T132	0	13	0	0
T134	0	1	0	0
T135	0	8	0	0
T136	0	6	0	0
T137	0	3	0	0
T138	15687	0	0	0
T139	17732	0	0	0
T140	21698	0	0	0
T141	22169	0	0	0
T142	885	0	0	0
T143	14888	0	0	0
T144	3196	0	0	0
T145	3797	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26106604	1251	0	0
T88	0	10	0	0
T90	0	11	0	0
T92	0	9	0	0
T99	97316	0	0	0
T125	962283	7	0	0
T130	0	9	0	0
T131	0	8	0	0
T132	0	16	0	0
T133	0	1	0	0
T134	0	6	0	0
T136	0	1	0	0
T138	15687	0	0	0
T139	17732	0	0	0
T140	21698	0	0	0
T141	22169	0	0	0
T142	885	0	0	0
T143	14888	0	0	0
T144	3196	0	0	0
T145	3797	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26106604	2268	0	0
T9	291221	1	0	0
T10	797	0	0	0
T11	15868	0	0	0
T12	789	0	0	0
T13	355093	0	0	0
T21	16926	0	0	0
T38	14943	0	0	0
T39	853	0	0	0
T80	10956	0	0	0
T85	3648	0	0	0
T90	0	5	0	0
T92	0	5	0	0
T125	0	17	0	0
T130	0	13	0	0
T131	0	2	0	0
T132	0	14	0	0
T134	0	9	0	0
T135	0	14	0	0
T136	0	22	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26106604	1335	0	0
T90	0	9	0	0
T92	0	2	0	0
T99	97316	0	0	0
T125	962283	14	0	0
T130	0	13	0	0
T131	0	13	0	0
T132	0	14	0	0
T133	0	1	0	0
T134	0	5	0	0
T135	0	8	0	0
T136	0	5	0	0
T138	15687	0	0	0
T139	17732	0	0	0
T140	21698	0	0	0
T141	22169	0	0	0
T142	885	0	0	0
T143	14888	0	0	0
T144	3196	0	0	0
T145	3797	0	0	0