Unified Coverage Report :: Module :: pwrmgr_reg_top

Module : pwrmgr_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_pwrmgr_reg_0.1/rtl/pwrmgr_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	96.01	97.63	100.00		92.53	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_cfg_cdc_sync	100.00	100.00	100.00			100.00
u_cfg_cdc_sync0_qe	100.00	100.00				100.00
u_chk	100.00	100.00		100.00			100.00
u_control_core_clk_en	100.00	100.00	100.00			100.00
u_control_io_clk_en	100.00	100.00	100.00			100.00
u_control_low_power_hint	100.00	100.00	100.00			100.00
u_control_main_pd_n	100.00	100.00	100.00			100.00
u_control_usb_clk_en_active	100.00	100.00	100.00			100.00
u_control_usb_clk_en_lp	100.00	100.00	100.00			100.00
u_ctrl_cfg_regwen	100.00	100.00
u_escalate_reset_status	62.59	77.78	50.00			60.00
u_fault_status_esc_timeout	96.30	88.89	100.00			100.00
u_fault_status_main_pd_glitch	100.00	100.00	100.00			100.00
u_fault_status_reg_intg_err	96.30	88.89	100.00			100.00
u_intr_enable	100.00	100.00	100.00			100.00
u_intr_state	100.00	100.00	100.00			100.00
u_intr_test	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_reset_en_en_0	100.00	100.00	100.00			100.00
u_reset_en_en_1	100.00	100.00	100.00			100.00
u_reset_en_regwen	100.00	100.00	100.00			100.00
u_reset_status_val_0	62.59	77.78	50.00			60.00
u_reset_status_val_1	62.59	77.78	50.00			60.00
u_rsp_intg_gen	100.00	100.00					100.00
u_wake_info_abort	100.00	100.00
u_wake_info_capture_dis	100.00	100.00	100.00			100.00
u_wake_info_fall_through	100.00	100.00
u_wake_info_reasons	100.00	100.00
u_wake_status_val_0	62.59	77.78	50.00			60.00
u_wake_status_val_1	62.59	77.78	50.00			60.00
u_wake_status_val_2	62.59	77.78	50.00			60.00
u_wake_status_val_3	62.59	77.78	50.00			60.00
u_wake_status_val_4	62.59	77.78	50.00			60.00
u_wake_status_val_5	62.59	77.78	50.00			60.00
u_wakeup_en_en_0	100.00	100.00	100.00			100.00
u_wakeup_en_en_1	100.00	100.00	100.00			100.00
u_wakeup_en_en_2	100.00	100.00	100.00			100.00
u_wakeup_en_en_3	100.00	100.00	100.00			100.00
u_wakeup_en_en_4	100.00	100.00	100.00			100.00
u_wakeup_en_en_5	100.00	100.00	100.00			100.00
u_wakeup_en_regwen	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_reg_top

	Line No.	Total	Covered	Percent
TOTAL		140	140	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
CONT_ASSIGN	521	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	917	1	1	100.00
CONT_ASSIGN	1089	1	1	100.00
CONT_ASSIGN	1104	1	1	100.00
CONT_ASSIGN	1120	1	1	100.00
CONT_ASSIGN	1136	1	1	100.00
ALWAYS	1228	18	18	100.00
CONT_ASSIGN	1248	1	1	100.00
ALWAYS	1252	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1275	1	1	100.00
CONT_ASSIGN	1276	1	1	100.00
CONT_ASSIGN	1278	1	1	100.00
CONT_ASSIGN	1279	1	1	100.00
CONT_ASSIGN	1281	1	1	100.00
CONT_ASSIGN	1282	1	1	100.00
CONT_ASSIGN	1284	1	1	100.00
CONT_ASSIGN	1285	1	1	100.00
CONT_ASSIGN	1286	1	1	100.00
CONT_ASSIGN	1288	1	1	100.00
CONT_ASSIGN	1290	1	1	100.00
CONT_ASSIGN	1292	1	1	100.00
CONT_ASSIGN	1294	1	1	100.00
CONT_ASSIGN	1296	1	1	100.00
CONT_ASSIGN	1298	1	1	100.00
CONT_ASSIGN	1299	1	1	100.00
CONT_ASSIGN	1301	1	1	100.00
CONT_ASSIGN	1302	1	1	100.00
CONT_ASSIGN	1304	1	1	100.00
CONT_ASSIGN	1305	1	1	100.00
CONT_ASSIGN	1307	1	1	100.00
CONT_ASSIGN	1309	1	1	100.00
CONT_ASSIGN	1311	1	1	100.00
CONT_ASSIGN	1313	1	1	100.00
CONT_ASSIGN	1315	1	1	100.00
CONT_ASSIGN	1317	1	1	100.00
CONT_ASSIGN	1318	1	1	100.00
CONT_ASSIGN	1320	1	1	100.00
CONT_ASSIGN	1321	1	1	100.00
CONT_ASSIGN	1323	1	1	100.00
CONT_ASSIGN	1325	1	1	100.00
CONT_ASSIGN	1326	1	1	100.00
CONT_ASSIGN	1328	1	1	100.00
CONT_ASSIGN	1329	1	1	100.00
CONT_ASSIGN	1330	1	1	100.00
CONT_ASSIGN	1332	1	1	100.00
CONT_ASSIGN	1334	1	1	100.00
CONT_ASSIGN	1336	1	1	100.00
ALWAYS	1340	18	18	100.00
ALWAYS	1362	40	40	100.00
CONT_ASSIGN	1464	0	0
CONT_ASSIGN	1472	1	1	100.00
CONT_ASSIGN	1473	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_pwrmgr_reg_0.1/rtl/pwrmgr_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_pwrmgr_reg_0.1/rtl/pwrmgr_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
79	1	1
91	1	1
92	1	1
120	1	1
121	1	1
264	1	1
278	1	1
284	1	1
298	1	1
320	1	1
521	1	1
556	1	1
917	1	1
1089	1	1
1104	1	1
1120	1	1
1136	1	1
1228	1	1
1229	1	1
1230	1	1
1231	1	1
1232	1	1
1233	1	1
1234	1	1
1235	1	1
1236	1	1
1237	1	1
1238	1	1
1239	1	1
1240	1	1
1241	1	1
1242	1	1
1243	1	1
1244	1	1
1245	1	1
1248	1	1
1252	1	1
1273	1	1
1275	1	1
1276	1	1
1278	1	1
1279	1	1
1281	1	1
1282	1	1
1284	1	1
1285	1	1
1286	1	1
1288	1	1
1290	1	1
1292	1	1
1294	1	1
1296	1	1
1298	1	1
1299	1	1
1301	1	1
1302	1	1
1304	1	1
1305	1	1
1307	1	1
1309	1	1
1311	1	1
1313	1	1
1315	1	1
1317	1	1
1318	1	1
1320	1	1
1321	1	1
1323	1	1
1325	1	1
1326	1	1
1328	1	1
1329	1	1
1330	1	1
1332	1	1
1334	1	1
1336	1	1
1340	1	1
1341	1	1
1342	1	1
1343	1	1
1344	1	1
1345	1	1
1346	1	1
1347	1	1
1348	1	1
1349	1	1
1350	1	1
1351	1	1
1352	1	1
1353	1	1
1354	1	1
1355	1	1
1356	1	1
1357	1	1
1362	1	1
1363	1	1
1365	1	1
1369	1	1
1373	1	1
1377	1	1
1381	1	1
1385	1	1
1386	1	1
1387	1	1
1388	1	1
1389	1	1
1390	1	1
1394	1	1
1398	1	1
1402	1	1
1403	1	1
1404	1	1
1405	1	1
1406	1	1
1407	1	1
1411	1	1
1412	1	1
1413	1	1
1414	1	1
1415	1	1
1416	1	1
1420	1	1
1424	1	1
1425	1	1
1429	1	1
1430	1	1
1434	1	1
1438	1	1
1442	1	1
1443	1	1
1444	1	1
1448	1	1
1449	1	1
1450	1	1
1464		unreachable
1472	1	1
1473	1	1

---

Cond Coverage for Module : pwrmgr_reg_top

	Total	Covered	Percent
Conditions	190	190	100.00
Logical	190	190	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T50,T47,T48
1	1	Covered	T2,T3,T4

 LINE       72
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T19
1	0	Covered	T47,T49,T54

 LINE       79
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T17,T18,T19
0	1	0	Covered	T47,T49,T54
1	0	0	Covered	T17,T18,T19

 LINE       121
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T47,T49,T54
0	1	0	Covered	T55,T50,T51
1	0	0	Covered	T50,T48,T56

 LINE       320
 EXPRESSION (control_we & ctrl_cfg_regwen_qs)
             -----1----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T57,T58,T59
1	1	Covered	T2,T5,T6

 LINE       556
 EXPRESSION (wakeup_en_we & wakeup_en_regwen_qs)
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T47,T60,T61
1	1	Covered	T2,T5,T6

 LINE       917
 EXPRESSION (reset_en_we & reset_en_regwen_qs)
             -----1-----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T47,T49,T62
1	1	Covered	T2,T3,T5

 LINE       1229
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_INTR_STATE_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1230
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_INTR_ENABLE_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1231
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_INTR_TEST_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       1232
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       1233
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_CTRL_CFG_REGWEN_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T9

 LINE       1234
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_CONTROL_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       1235
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_CFG_CDC_SYNC_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1236
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_REGWEN_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       1237
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_WAKEUP_EN_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       1238
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_WAKE_STATUS_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       1239
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_RESET_EN_REGWEN_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       1240
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_RESET_EN_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1241
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_RESET_STATUS_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1242
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_ESCALATE_RESET_STATUS_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       1243
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1244
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_WAKE_INFO_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       1245
 EXPRESSION (reg_addr == pwrmgr_reg_pkg::PWRMGR_FAULT_STATUS_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       1248
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1248
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       1252
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T55,T50,T51

 LINE       1252
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	Status	Tests
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T2,T3,T4
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	Covered	T2,T4,T5
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	Covered	T2,T4,T5
0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	Covered	T2,T4,T5
0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	Covered	T2,T4,T5
0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	Covered	T2,T3,T4
0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	Covered	T2,T4,T5
0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	Covered	T2,T4,T5
0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	Covered	T2,T4,T5
0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	Covered	T2,T4,T5
0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	Covered	T4,T5,T9
0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	Covered	T2,T3,T4
0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	Covered	T2,T4,T5
0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T4,T5,T9
0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T2,T4,T5
0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T2,T4,T5
0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T4,T5,T9
1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T4

 LINE       1252
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T4

 LINE       1252
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T4,T5,T9

 LINE       1252
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T9
1	1	Covered	T2,T4,T5

 LINE       1252
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       1252
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T9
1	1	Covered	T4,T5,T9

 LINE       1252
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T4,T5

 LINE       1252
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       1252
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T9
1	1	Covered	T4,T5,T9

 LINE       1252
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       1252
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       1252
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T9
1	1	Covered	T2,T4,T5

 LINE       1252
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T4,T5

 LINE       1252
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T3,T4

 LINE       1252
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

 LINE       1252
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T4,T5

 LINE       1252
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T4,T5

 LINE       1252
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T9
1	1	Covered	T2,T4,T5

 LINE       1273
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T48,T56,T63
1	1	1	Covered	T2,T3,T4

 LINE       1276
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T48,T64,T65
1	1	1	Covered	T2,T3,T4

 LINE       1279
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T48,T56,T65
1	1	1	Covered	T66,T67,T68

 LINE       1282
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T48,T56,T65
1	1	1	Covered	T47,T69,T70

 LINE       1285
 EXPRESSION (addr_hit[4] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T9
1	1	0	Covered	T71,T64,T72
1	1	1	Covered	T9,T13,T50

 LINE       1286
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T48,T56,T73
1	1	1	Covered	T2,T5,T6

 LINE       1299
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T48,T61,T56
1	1	1	Covered	T2,T3,T5

 LINE       1302
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T74,T56,T65
1	1	1	Covered	T47,T69,T70

 LINE       1305
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T48,T56,T65
1	1	1	Covered	T2,T5,T6

 LINE       1318
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T2,T4,T5
1	1	0	Covered	T47,T64,T75
1	1	1	Covered	T47,T69,T70

 LINE       1321
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T48,T56,T76
1	1	1	Covered	T2,T3,T5

 LINE       1326
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T48,T56,T77
1	1	1	Covered	T2,T3,T4

 LINE       1329
 EXPRESSION (addr_hit[15] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T78
1	1	1	Covered	T2,T3,T4

 LINE       1330
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T48,T61,T62
1	1	1	Covered	T2,T3,T4

---

Branch Coverage for Module : pwrmgr_reg_top

	Line No.	Total	Covered	Percent
Branches		23	23	100.00
TERNARY	1248	2	2	100.00
IF	70	3	3	100.00
CASE	1363	18	18	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_pwrmgr_reg_0.1/rtl/pwrmgr_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_pwrmgr_reg_0.1/rtl/pwrmgr_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1248	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_lc_ni))
-2-:	72	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T17,T18,T19
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1363	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T3,T4
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	26106604	716929	0	0
reAfterRv	26106604	716928	0	0
rePulse	26106604	377966	0	0
wePulse	26106604	338962	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	26106604	716929	0	0
T1	2272	1	0	0
T2	6056	94	0	0
T3	3034	31	0	0
T4	4820	244	0	0
T5	45335	2081	0	0
T6	1551	41	0	0
T7	18503	314	0	0
T8	14230	862	0	0
T9	291221	5071	0	0
T10	797	1	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	26106604	716928	0	0
T1	2272	1	0	0
T2	6056	94	0	0
T3	3034	31	0	0
T4	4820	244	0	0
T5	45335	2081	0	0
T6	1551	41	0	0
T7	18503	314	0	0
T8	14230	862	0	0
T9	291221	5071	0	0
T10	797	1	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	26106604	377966	0	0
T1	2272	1	0	0
T2	6056	47	0	0
T3	3034	21	0	0
T4	4820	182	0	0
T5	45335	1188	0	0
T6	1551	31	0	0
T7	18503	170	0	0
T8	14230	410	0	0
T9	291221	2631	0	0
T10	797	1	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	26106604	338962	0	0
T2	6056	47	0	0
T3	3034	10	0	0
T4	4820	62	0	0
T5	45335	893	0	0
T6	1551	10	0	0
T7	18503	144	0	0
T8	14230	452	0	0
T9	291221	2440	0	0
T10	797	0	0	0
T11	15868	0	0	0
T13	0	3480	0	0
T21	0	452	0	0