Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	76545636	148998	0	0
StatusRise_A	76545636	166217	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76545636	148998	0	0
T2	18168	18	0	0
T3	9102	12	0	0
T4	14460	3	0	0
T5	136005	463	0	0
T6	4653	6	0	0
T7	55509	56	0	0
T8	42690	212	0	0
T9	873663	1277	0	0
T10	2391	3	0	0
T11	47604	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76545636	166217	0	0
T1	6816	9	0	0
T2	18168	20	0	0
T3	9102	18	0	0
T4	14460	6	0	0
T5	136005	499	0	0
T6	4653	9	0	0
T7	55509	59	0	0
T8	42690	218	0	0
T9	873663	1401	0	0
T10	2391	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25515212	55336	0	0
StatusRise_A	25515212	61563	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25515212	55336	0	0
T2	6056	7	0	0
T3	3034	4	0	0
T4	4820	1	0	0
T5	45335	165	0	0
T6	1551	2	0	0
T7	18503	20	0	0
T8	14230	86	0	0
T9	291221	458	0	0
T10	797	1	0	0
T11	15868	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25515212	61563	0	0
T1	2272	3	0	0
T2	6056	8	0	0
T3	3034	6	0	0
T4	4820	2	0	0
T5	45335	178	0	0
T6	1551	3	0	0
T7	18503	21	0	0
T8	14230	88	0	0
T9	291221	504	0	0
T10	797	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25515212	55336	0	0
StatusRise_A	25515212	61563	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25515212	55336	0	0
T2	6056	7	0	0
T3	3034	4	0	0
T4	4820	1	0	0
T5	45335	165	0	0
T6	1551	2	0	0
T7	18503	20	0	0
T8	14230	86	0	0
T9	291221	458	0	0
T10	797	1	0	0
T11	15868	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25515212	61563	0	0
T1	2272	3	0	0
T2	6056	8	0	0
T3	3034	6	0	0
T4	4820	2	0	0
T5	45335	178	0	0
T6	1551	3	0	0
T7	18503	21	0	0
T8	14230	88	0	0
T9	291221	504	0	0
T10	797	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25515212	38326	0	0
StatusRise_A	25515212	43091	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25515212	38326	0	0
T2	6056	4	0	0
T3	3034	4	0	0
T4	4820	1	0	0
T5	45335	133	0	0
T6	1551	2	0	0
T7	18503	16	0	0
T8	14230	40	0	0
T9	291221	361	0	0
T10	797	1	0	0
T11	15868	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25515212	43091	0	0
T1	2272	3	0	0
T2	6056	4	0	0
T3	3034	6	0	0
T4	4820	2	0	0
T5	45335	143	0	0
T6	1551	3	0	0
T7	18503	17	0	0
T8	14230	42	0	0
T9	291221	393	0	0
T10	797	3	0	0