Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	25515795	6158	0	0
EscTimeoutStoppedByClReset_A	25515212	3603959	0	0
EscTimeoutTriggersReset_A	5274534	317	0	0
RomAllowActiveState_A	25515212	61180	0	0
RomAllowCheckGoodState_A	25515212	61230	0	0
RomBlockActiveState_A	25515212	26510	0	0
RomBlockCheckGoodState_A	25515212	408034	0	0
RomIntgChkDisFalse_A	25515212	24856257	0	0
RomIntgChkDisTrue_A	25515212	123807	0	0
RstreqChkEsctimeout_A	25515212	4452	0	0
RstreqChkFsmterm_A	25515212	180	0	0
RstreqChkGlbesc_A	25515212	4452	0	0
RstreqChkMainpd_A	25515212	988152	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25515795	6158	0	0
T10	798	7	0	0
T11	15868	242	0	0
T12	790	0	0	0
T13	355094	0	0	0
T14	2413	0	0	0
T21	16927	0	0	0
T38	14944	55	0	0
T39	854	0	0	0
T40	0	56	0	0
T80	10957	0	0	0
T85	3648	0	0	0
T146	0	116	0	0
T147	0	217	0	0
T148	0	73	0	0
T149	0	257	0	0
T150	0	25	0	0
T151	0	12	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25515212	3603959	0	0
T1	2272	28	0	0
T2	6056	1466	0	0
T3	3034	224	0	0
T4	4820	13	0	0
T5	45335	5999	0	0
T6	1551	16	0	0
T7	18503	3180	0	0
T8	14230	2940	0	0
T9	291221	46642	0	0
T10	797	17	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5274534	317	0	0
T10	264	5	0	0
T11	205	3	0	0
T12	269	5	0	0
T13	36221	0	0	0
T14	231	0	0	0
T21	6483	0	0	0
T38	671	3	0	0
T39	269	5	0	0
T40	0	3	0	0
T80	1113	0	0	0
T85	3668	0	0	0
T146	0	2	0	0
T147	0	3	0	0
T148	0	2	0	0
T152	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25515212	61180	0	0
T1	2272	3	0	0
T2	6056	8	0	0
T3	3034	6	0	0
T4	4820	2	0	0
T5	45335	178	0	0
T6	1551	3	0	0
T7	18503	21	0	0
T8	14230	88	0	0
T9	291221	504	0	0
T10	797	3	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25515212	61230	0	0
T1	2272	3	0	0
T2	6056	8	0	0
T3	3034	6	0	0
T4	4820	2	0	0
T5	45335	178	0	0
T6	1551	3	0	0
T7	18503	21	0	0
T8	14230	88	0	0
T9	291221	504	0	0
T10	797	3	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25515212	26510	0	0
T22	13403	14	0	0
T25	0	239	0	0
T29	0	8	0	0
T33	0	6	0	0
T46	2000	295	0	0
T59	8029	0	0	0
T79	23093	0	0	0
T83	1729	0	0	0
T84	4445	0	0	0
T127	1991	0	0	0
T139	0	25	0	0
T140	0	15	0	0
T147	15857	0	0	0
T152	2441	0	0	0
T153	0	1192	0	0
T154	0	1110	0	0
T155	0	2	0	0
T156	5330	0	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25515212	408034	0	0
T2	6056	114	0	0
T3	3034	0	0	0
T4	4820	0	0	0
T5	45335	803	0	0
T6	1551	0	0	0
T7	18503	0	0	0
T8	14230	1067	0	0
T9	291221	1424	0	0
T10	797	0	0	0
T11	15868	0	0	0
T13	0	2363	0	0
T21	0	1346	0	0
T22	0	927	0	0
T35	0	642	0	0
T46	0	77	0	0
T157	0	46	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25515212	24856257	0	0
T1	2272	2005	0	0
T2	6056	5961	0	0
T3	3034	2898	0	0
T4	4820	4735	0	0
T5	45335	44353	0	0
T6	1551	1500	0	0
T7	18503	18452	0	0
T8	14230	5357	0	0
T9	291221	288073	0	0
T10	797	675	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25515212	123807	0	0
T8	14230	8758	0	0
T9	291221	0	0	0
T10	797	0	0	0
T11	15868	0	0	0
T12	789	0	0	0
T13	355093	0	0	0
T21	16926	12	0	0
T22	0	534	0	0
T25	0	226	0	0
T38	14943	0	0	0
T46	0	164	0	0
T80	10956	0	0	0
T85	3648	0	0	0
T153	0	412	0	0
T154	0	184	0	0
T158	0	1583	0	0
T159	0	2115	0	0
T160	0	216	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25515212	4452	0	0
T1	2272	2	0	0
T2	6056	0	0	0
T3	3034	2	0	0
T4	4820	0	0	0
T5	45335	13	0	0
T6	1551	0	0	0
T7	18503	0	0	0
T8	14230	0	0	0
T9	291221	49	0	0
T10	797	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	34	0	0
T38	0	1	0	0
T39	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25515212	180	0	0
T17	24860	40	0	0
T18	0	40	0	0
T19	0	20	0	0
T23	0	40	0	0
T24	0	40	0	0
T25	1798	0	0	0
T26	1728	0	0	0
T27	3648	0	0	0
T28	1520	0	0	0
T29	17406	0	0	0
T30	16513	0	0	0
T31	13871	0	0	0
T32	494	0	0	0
T33	17807	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25515212	4452	0	0
T1	2272	2	0	0
T2	6056	0	0	0
T3	3034	2	0	0
T4	4820	0	0	0
T5	45335	13	0	0
T6	1551	0	0	0
T7	18503	0	0	0
T8	14230	0	0	0
T9	291221	49	0	0
T10	797	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	34	0	0
T38	0	1	0	0
T39	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25515212	988152	0	0
T3	3034	193	0	0
T4	4820	0	0	0
T5	45335	3836	0	0
T6	1551	0	0	0
T7	18503	0	0	0
T8	14230	1254	0	0
T9	291221	11425	0	0
T10	797	0	0	0
T11	15868	0	0	0
T13	355093	14428	0	0
T14	0	5	0	0
T21	0	2487	0	0
T34	0	85	0	0
T35	0	2265	0	0
T36	0	84	0	0