Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31776

1

T1

5

T5

48

T6

48

auto[1]

30393

1

T1

2

T5

52

T6

52

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31803

1

T1

7

T5

56

T6

46

auto[1]

30366

1

T5

44

T6

54

T10

48

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30432

1

T1

5

T5

48

T6

50

auto[1]

31737

1

T1

2

T5

52

T6

50

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34647

1

T1

7

T5

50

T6

50

auto[1]

27522

1

T5

50

T6

50

T8

1

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30309

1

T1

3

T5

42

T6

42

auto[1]

31860

1

T1

4

T5

58

T6

58

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31964

1

T1

3

T5

48

T6

58

auto[1]

30205

1

T1

4

T5

52

T6

42

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1060

1

T1

1

T6

1

T10

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

854

1

T6

1

T10

3

T24

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1070

1

T6

1

T10

3

T24

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

832

1

T6

1

T10

3

T24

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1091

1

T5

2

T6

5

T10

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

852

1

T5

2

T6

5

T10

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1812

1

T1

1

T5

4

T6

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1582

1

T5

4

T6

3

T8

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1056

1

T5

3

T6

1

T10

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

838

1

T5

3

T6

1

T10

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1041

1

T1

1

T5

2

T24

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

820

1

T5

2

T24

2

T25

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1038

1

T1

2

T5

2

T10

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

801

1

T5

2

T10

2

T24

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1045

1

T5

2

T24

1

T25

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

828

1

T5

2

T24

1

T25

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1050

1

T10

1

T24

2

T25

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

831

1

T10

1

T24

2

T25

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1028

1

T5

1

T6

1

T10

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

809

1

T5

1

T6

1

T10

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1080

1

T5

2

T6

2

T10

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

837

1

T5

2

T6

2

T10

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1066

1

T5

2

T6

4

T10

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

828

1

T5

2

T6

4

T10

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1103

1

T6

1

T10

1

T24

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

873

1

T6

1

T10

1

T24

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1053

1

T24

2

T60

1

T65

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

820

1

T24

2

T60

1

T65

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1067

1

T5

1

T6

3

T10

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

862

1

T5

1

T6

3

T10

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1033

1

T5

3

T6

2

T10

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

816

1

T5

3

T6

2

T10

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1067

1

T1

1

T5

2

T6

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

839

1

T5

2

T6

1

T10

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1073

1

T5

3

T6

3

T10

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

852

1

T5

3

T6

3

T10

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1043

1

T5

1

T6

1

T25

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

840

1

T5

1

T6

1

T25

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1080

1

T5

2

T6

1

T10

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

860

1

T5

2

T6

1

T10

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

985

1

T5

3

T6

2

T10

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

788

1

T5

3

T6

2

T10

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1072

1

T6

1

T10

1

T24

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

849

1

T6

1

T10

1

T24

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1035

1

T1

1

T5

2

T6

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

835

1

T5

2

T6

3

T24

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1090

1

T10

4

T25

3

T26

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

875

1

T10

4

T25

3

T26

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1049

1

T5

2

T10

2

T24

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

827

1

T5

2

T10

2

T24

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1086

1

T5

1

T6

4

T10

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

860

1

T5

1

T6

4

T10

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1055

1

T5

2

T6

1

T10

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

826

1

T5

2

T6

1

T10

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1071

1

T6

1

T10

1

T40

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

854

1

T6

1

T10

1

T40

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1122

1

T5

2

T6

3

T25

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

893

1

T5

2

T6

3

T25

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1023

1

T5

2

T6

2

T10

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

786

1

T5

2

T6

2

T10

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1081

1

T6

1

T24

1

T25

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

854

1

T6

1

T24

1

T25

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1022

1

T5

4

T6

2

T10

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

801

1

T5

4

T6

2

T10

1