---

Detail Report for Assertions

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertNumCheck_A	0	0	955	955	0	0
tb.dut.AlertsKnownO_A	0	0	26052880	25529236	0	0
tb.dut.AstKnownO_A	0	0	26052880	25529236	0	0
tb.dut.ClkKnownO_A	0	0	26052880	25529236	0	0
tb.dut.ClkRatio_A	0	0	26052880	25529236	0	0
tb.dut.FpvSecCmFsmCheck_A	0	0	26052880	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	26052880	80	0	0
tb.dut.FpvSecCmSlowFsmCheck_A	0	0	4730312	80	0	0
tb.dut.GlitchStatusPersist_A	0	0	26052880	6357	0	0
tb.dut.IntrKnownO_A	0	0	26052880	25529236	0	0
tb.dut.LcKnownO_A	0	0	26052880	25529236	0	0
tb.dut.OtpKnownO_A	0	0	26052880	25529236	0	0
tb.dut.PwrmgrSecCmEscToLCReset_A	0	0	26052880	2362	0	0
tb.dut.PwrmgrSecCmEscToSlowResetReq_A	0	0	4730312	14154	0	0
tb.dut.PwrmgrSecCmFsmEscToResetReq_A	0	0	26052880	110073	0	0
tb.dut.RstKnownO_A	0	0	26052880	25529236	0	0
tb.dut.TlAReadyKnownO_A	0	0	26052880	25529236	0	0
tb.dut.TlDValidKnownO_A	0	0	26052880	25529236	0	0
tb.dut.clkmgr_pwrmgr_io_sva_if.StatusFall_A	0	0	26052880	54377	0	0
tb.dut.clkmgr_pwrmgr_io_sva_if.StatusRise_A	0	0	26052880	60431	0	0
tb.dut.clkmgr_pwrmgr_main_sva_if.StatusFall_A	0	0	26052880	54377	0	0
tb.dut.clkmgr_pwrmgr_main_sva_if.StatusRise_A	0	0	26052880	60441	0	0
tb.dut.clkmgr_pwrmgr_usb_sva_if.StatusFall_A	0	0	26052880	37968	0	0
tb.dut.clkmgr_pwrmgr_usb_sva_if.StatusRise_A	0	0	26052880	42640	0	0
tb.dut.intr_wakeup.IntrTKind_A	0	0	955	955	0	0
tb.dut.pwrmgr_clock_enables_sva_if.CoreClkPwrDown_A	0	0	4730312	14054	0	0
tb.dut.pwrmgr_clock_enables_sva_if.CoreClkPwrUp_A	0	0	4730312	163655	0	0
tb.dut.pwrmgr_clock_enables_sva_if.IoClkPwrDown_A	0	0	4730312	14054	0	0
tb.dut.pwrmgr_clock_enables_sva_if.IoClkPwrUp_A	0	0	4730312	163655	0	0
tb.dut.pwrmgr_clock_enables_sva_if.UsbClkActive_A	0	0	4730312	3214	0	0
tb.dut.pwrmgr_clock_enables_sva_if.UsbClkPwrDown_A	0	0	4730312	14054	0	0
tb.dut.pwrmgr_clock_enables_sva_if.UsbClkPwrUp_A	0	0	4730312	163655	0	0
tb.dut.pwrmgr_csr_assert.TlulOOBAddrErr_A	0	0	26607971	14932	0	0
tb.dut.pwrmgr_csr_assert.intr_enable_rd_A	0	0	26607971	30037	0	0
tb.dut.pwrmgr_csr_assert.reset_en_rd_A	0	0	26607971	1590	0	0
tb.dut.pwrmgr_csr_assert.reset_en_regwen_rd_A	0	0	26607971	1396	0	0
tb.dut.pwrmgr_csr_assert.wake_info_capture_dis_rd_A	0	0	26607971	1334	0	0
tb.dut.pwrmgr_csr_assert.wakeup_en_rd_A	0	0	26607971	2331	0	0
tb.dut.pwrmgr_csr_assert.wakeup_en_regwen_rd_A	0	0	26607971	1311	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOff_A	0	0	26052880	6094	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOn_A	0	0	26052880	272644	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOff_A	0	0	26052880	10764644	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOn_A	0	0	26052880	272653	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOff_A	0	0	26052880	6094	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOn_A	0	0	26052880	272644	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOff_A	0	0	26052880	10764644	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOn_A	0	0	26052880	272653	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.EscClkStopEscTimeout_A	0	0	26053468	5823	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.EscTimeoutStoppedByClReset_A	0	0	26052880	3808476	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.EscTimeoutTriggersReset_A	0	0	4730312	315	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RomAllowActiveState_A	0	0	26052880	60052	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RomAllowCheckGoodState_A	0	0	26052880	60102	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RomBlockActiveState_A	0	0	26052880	31003	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RomBlockCheckGoodState_A	0	0	26052880	418982	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RomIntgChkDisFalse_A	0	0	26052880	25383797	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RomIntgChkDisTrue_A	0	0	26052880	145439	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RstreqChkEsctimeout_A	0	0	26052880	4496	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RstreqChkFsmterm_A	0	0	26052880	160	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RstreqChkGlbesc_A	0	0	26052880	4496	0	0
tb.dut.pwrmgr_sec_cm_checker_assert.RstreqChkMainpd_A	0	0	26052880	1077657	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	26607971	803910	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	26607971	26047222	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	26607971	26047222	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	26607971	1174498	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	26607971	26047222	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	26607971	26047222	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
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tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
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tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
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tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
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tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
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tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
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tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
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tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
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tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
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tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
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tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
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tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
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tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
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tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	1120	1120	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	26608646	380728	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	26607971	5337	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	26608646	200087	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	26608646	236969	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	26607971	6046	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	26608646	803971	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	26608646	1174542	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	26608646	803971	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	26608646	1174542	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	26608646	1174542	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	26608646	1174542	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	26607971	3296	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	26607971	2260	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	1120	1120	0	0
tb.dut.u_cdc.u_scdc_sync.DstPulseCheck_A	0	0	26052880	43161	0	0
tb.dut.u_cdc.u_scdc_sync.SrcPulseCheck_M	0	0	4730312	43190	0	0
tb.dut.u_cdc.u_slow_cdc_sync.DstPulseCheck_A	0	0	4730312	43169	0	0
tb.dut.u_cdc.u_slow_cdc_sync.SrcPulseCheck_M	0	0	26052880	43265	0	0
tb.dut.u_cdc.u_sync_rom_ctrl.NumCopiesMustBeGreaterZero_A	0	0	955	955	0	0
tb.dut.u_cdc.u_sync_rom_ctrl.OutputsKnown_A	0	0	22598589	22078767	0	0
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.OutputDelay_A	0	0	22598589	22058214	0	2565
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	22598589	32877	0	0
tb.dut.u_esc_timeout.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	20044545	2267565	0	0
tb.dut.u_fsm.AlwaysOnIndex_A	0	0	955	955	0	0
tb.dut.u_fsm.u_state_regs.AssertConnected_A	0	0	955	955	0	0
tb.dut.u_fsm.u_state_regs_A	0	0	26052880	25529236	0	0
tb.dut.u_prim_lc_sync_dft_en.NumCopiesMustBeGreaterZero_A	0	0	955	955	0	0
tb.dut.u_prim_lc_sync_dft_en.OutputsKnown_A	0	0	26052880	25529236	0	0
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A	0	0	26052880	25508236	0	2865
tb.dut.u_prim_lc_sync_hw_debug_en.NumCopiesMustBeGreaterZero_A	0	0	955	955	0	0
tb.dut.u_prim_lc_sync_hw_debug_en.OutputsKnown_A	0	0	26052880	25529236	0	0
tb.dut.u_prim_lc_sync_hw_debug_en.gen_flops.OutputDelay_A	0	0	26052880	25508236	0	2865
tb.dut.u_reg.en2addrHit	0	0	26607971	710987	0	0
tb.dut.u_reg.reAfterRv	0	0	26607971	710985	0	0
tb.dut.u_reg.rePulse	0	0	26607971	384499	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	1120	1120	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	1120	1120	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	1120	1120	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	1120	1120	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1120	1120	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1120	1120	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	1120	1120	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1120	1120	0	0
tb.dut.u_reg.wePulse	0	0	26607971	326486	0	0
tb.dut.u_slow_fsm.IntRstReq_A	0	0	625706	615477	0	0
tb.dut.u_slow_fsm.u_state_regs.AssertConnected_A	0	0	955	955	0	0
tb.dut.u_slow_fsm.u_state_regs_A	0	0	4730312	4695241	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.OutputDelay_A	0	0	22598589	22058214	0	2565
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A	0	0	26052880	25508236	0	2865
tb.dut.u_prim_lc_sync_hw_debug_en.gen_flops.OutputDelay_A	0	0	26052880	25508236	0	2865

Assertions Excluded:

ASSERTIONS	CATEGORY	SEVERITY	EXCLUSION	EXCLUDE ANNOTATION	SRC
tb.dut.u_esc_timeout.u_ref_timeout.SyncReqAckHoldReq	0	0	Excluded	[UNR] Input req_chk_i is tied to constant 0 and src_req_i to constant 1

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	26608646	754	754	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	26608646	80	80	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	26608646	86	86	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	26608646	54	54	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	26608646	7	7	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	26608646	49	49	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	26608646	41	41	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	26608646	1635	1635	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	26608646	7067	7067	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	26608646	132040	132040	1050

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	26608646	754	754	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	26608646	80	80	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	26608646	86	86	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	26608646	54	54	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	26608646	7	7	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	26608646	49	49	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	26608646	41	41	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	26608646	1635	1635	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	26608646	7067	7067	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	26608646	132040	132040	1050