Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	513701	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

197079

1

T2

1

T3

6

T4

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	371036	1			T1	1		T2	1		T3	11
values[0x0]	169444	1			T3	2		T4	7		T5	11
values[0x1]	170300	1			T3	4		T4	9		T5	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	406832	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

303948

1

T1

1

T2

1

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2493	1			T6	1		T13	20		T38	2
valid_sources[0x01]	2962	1			T6	1		T8	1		T13	16
valid_sources[0x02]	2773	1			T5	2		T8	1		T13	11
valid_sources[0x03]	2547	1			T13	26		T38	1		T21	5
valid_sources[0x04]	2279	1			T6	1		T8	1		T13	17
valid_sources[0x05]	3716	1			T8	1		T13	16		T21	4
valid_sources[0x06]	2401	1			T5	2		T8	1		T13	14
valid_sources[0x07]	3439	1			T5	2		T6	1		T8	1
valid_sources[0x08]	2592	1			T6	1		T8	3		T13	17
valid_sources[0x09]	2500	1			T6	1		T13	25		T34	2
valid_sources[0x0a]	2578	1			T13	11		T14	43		T15	17
valid_sources[0x0b]	2325	1			T6	2		T13	20		T21	6
valid_sources[0x0c]	2325	1			T6	1		T8	4		T13	19
valid_sources[0x0d]	2440	1			T6	2		T13	21		T38	1
valid_sources[0x0e]	2245	1			T13	17		T21	3		T34	1
valid_sources[0x0f]	2891	1			T13	26		T34	2		T61	1
valid_sources[0x10]	2472	1			T6	1		T13	11		T38	2
valid_sources[0x11]	3079	1			T6	2		T8	3		T13	12
valid_sources[0x12]	2429	1			T6	1		T8	4		T13	25
valid_sources[0x13]	2436	1			T13	15		T21	5		T34	3
valid_sources[0x14]	2495	1			T8	1		T13	12		T21	1
valid_sources[0x15]	2867	1			T6	2		T13	17		T38	1
valid_sources[0x16]	2464	1			T6	1		T13	24		T34	1
valid_sources[0x17]	2475	1			T8	6		T13	20		T57	1
valid_sources[0x18]	2535	1			T13	13		T21	2		T14	27
valid_sources[0x19]	2291	1			T6	1		T8	1		T13	8
valid_sources[0x1a]	3508	1			T6	1		T13	17		T21	3
valid_sources[0x1b]	2370	1			T6	3		T8	2		T13	20
valid_sources[0x1c]	3661	1			T4	1		T6	1		T8	1
valid_sources[0x1d]	3034	1			T6	1		T13	12		T21	5
valid_sources[0x1e]	2908	1			T6	1		T8	2		T13	18
valid_sources[0x1f]	2457	1			T6	2		T8	1		T13	18
valid_sources[0x20]	2503	1			T6	1		T8	3		T13	15
valid_sources[0x21]	2565	1			T6	1		T10	129		T13	20
valid_sources[0x22]	2412	1			T4	2		T5	4		T13	12
valid_sources[0x23]	2755	1			T8	2		T13	30		T38	1
valid_sources[0x24]	3840	1			T13	19		T21	2		T34	2
valid_sources[0x25]	3196	1			T6	2		T8	1		T13	18
valid_sources[0x26]	4570	1			T13	31		T21	2		T34	1
valid_sources[0x27]	3223	1			T13	23		T21	3		T34	1
valid_sources[0x28]	2174	1			T6	1		T8	1		T13	20
valid_sources[0x29]	3441	1			T5	3		T13	14		T21	3
valid_sources[0x2a]	2562	1			T6	2		T8	1		T13	21
valid_sources[0x2b]	3162	1			T8	3		T13	22		T21	7
valid_sources[0x2c]	2303	1			T5	2		T6	2		T13	19
valid_sources[0x2d]	2708	1			T6	2		T8	2		T13	12
valid_sources[0x2e]	2224	1			T13	16		T21	7		T61	1
valid_sources[0x2f]	3511	1			T6	2		T8	2		T13	11
valid_sources[0x30]	2777	1			T1	1		T13	20		T61	2
valid_sources[0x31]	2349	1			T6	1		T8	3		T13	20
valid_sources[0x32]	2428	1			T4	1		T5	1		T6	1
valid_sources[0x33]	3109	1			T6	2		T13	9		T21	6
valid_sources[0x34]	2275	1			T13	12		T34	2		T57	2
valid_sources[0x35]	2139	1			T6	1		T8	2		T13	23
valid_sources[0x36]	2281	1			T6	1		T8	3		T13	20
valid_sources[0x37]	2476	1			T13	21		T34	1		T14	43
valid_sources[0x38]	2571	1			T5	1		T8	2		T13	18
valid_sources[0x39]	2405	1			T6	1		T13	27		T21	3
valid_sources[0x3a]	2657	1			T8	3		T13	24		T38	1
valid_sources[0x3b]	2372	1			T5	3		T6	2		T13	17
valid_sources[0x3c]	2418	1			T6	1		T8	4		T13	21
valid_sources[0x3d]	2906	1			T6	1		T8	2		T13	17
valid_sources[0x3e]	2392	1			T13	12		T21	1		T57	1
valid_sources[0x3f]	3408	1			T8	1		T13	17		T34	3
valid_sources[0x40]	3712	1			T5	1		T8	1		T13	22
valid_sources[0x41]	2750	1			T6	1		T8	2		T13	21
valid_sources[0x42]	2783	1			T6	1		T13	17		T21	1
valid_sources[0x43]	2575	1			T6	1		T8	1		T13	20
valid_sources[0x44]	2534	1			T13	15		T21	6		T34	5
valid_sources[0x45]	2147	1			T6	1		T8	2		T13	18
valid_sources[0x46]	3093	1			T4	1		T6	1		T8	1
valid_sources[0x47]	2611	1			T13	15		T38	1		T21	10
valid_sources[0x48]	2329	1			T6	2		T8	2		T13	13
valid_sources[0x49]	2550	1			T13	17		T21	6		T34	1
valid_sources[0x4a]	2375	1			T13	22		T34	2		T14	38
valid_sources[0x4b]	2339	1			T4	1		T5	2		T6	1
valid_sources[0x4c]	2432	1			T5	3		T13	16		T38	1
valid_sources[0x4d]	3884	1			T6	1		T8	1		T13	24
valid_sources[0x4e]	2512	1			T8	1		T13	18		T21	6
valid_sources[0x4f]	2334	1			T13	10		T21	3		T34	1
valid_sources[0x50]	2800	1			T6	1		T8	2		T13	21
valid_sources[0x51]	2467	1			T6	1		T13	12		T21	1
valid_sources[0x52]	3135	1			T6	1		T8	1		T13	26
valid_sources[0x53]	2155	1			T5	5		T6	1		T8	1
valid_sources[0x54]	2687	1			T6	1		T8	2		T13	12
valid_sources[0x55]	2401	1			T8	3		T13	21		T14	39
valid_sources[0x56]	2377	1			T6	1		T13	20		T21	8
valid_sources[0x57]	2937	1			T6	1		T8	1		T13	17
valid_sources[0x58]	2730	1			T5	6		T6	1		T8	1
valid_sources[0x59]	2784	1			T6	1		T8	1		T13	11
valid_sources[0x5a]	2489	1			T8	4		T13	19		T21	6
valid_sources[0x5b]	2572	1			T6	1		T8	3		T13	8
valid_sources[0x5c]	3369	1			T6	1		T13	16		T21	2
valid_sources[0x5d]	2114	1			T8	1		T13	16		T38	1
valid_sources[0x5e]	2518	1			T3	14		T5	1		T13	15
valid_sources[0x5f]	3296	1			T6	2		T8	1		T13	15
valid_sources[0x60]	2391	1			T5	2		T6	1		T8	1
valid_sources[0x61]	2825	1			T6	1		T8	2		T13	30
valid_sources[0x62]	2836	1			T13	22		T38	1		T21	1
valid_sources[0x63]	3260	1			T4	1		T6	1		T8	4
valid_sources[0x64]	3929	1			T6	1		T8	3		T13	16
valid_sources[0x65]	2902	1			T4	1		T6	1		T13	19
valid_sources[0x66]	2656	1			T13	28		T34	2		T61	1
valid_sources[0x67]	2253	1			T4	1		T6	1		T13	19
valid_sources[0x68]	2459	1			T6	2		T13	17		T21	13
valid_sources[0x69]	2299	1			T6	2		T13	23		T21	18
valid_sources[0x6a]	2416	1			T13	14		T34	1		T61	1
valid_sources[0x6b]	2579	1			T8	1		T13	21		T21	2
valid_sources[0x6c]	2536	1			T6	2		T13	20		T21	2
valid_sources[0x6d]	2213	1			T13	14		T21	2		T34	1
valid_sources[0x6e]	2353	1			T5	4		T13	21		T21	7
valid_sources[0x6f]	2510	1			T5	4		T8	2		T13	17
valid_sources[0x70]	2365	1			T5	4		T6	1		T8	2
valid_sources[0x71]	2917	1			T6	2		T8	1		T13	12
valid_sources[0x72]	2569	1			T8	1		T13	22		T21	7
valid_sources[0x73]	3605	1			T6	3		T8	2		T13	21
valid_sources[0x74]	2809	1			T13	22		T21	19		T34	1
valid_sources[0x75]	3612	1			T6	1		T8	1		T13	16
valid_sources[0x76]	3397	1			T6	1		T8	1		T13	9
valid_sources[0x77]	2043	1			T13	21		T34	3		T77	1
valid_sources[0x78]	2454	1			T6	2		T8	2		T13	16
valid_sources[0x79]	3205	1			T6	1		T13	20		T21	4
valid_sources[0x7a]	3709	1			T4	1		T8	2		T13	20
valid_sources[0x7b]	2323	1			T6	1		T8	1		T13	24
valid_sources[0x7c]	2247	1			T4	2		T6	1		T13	17
valid_sources[0x7d]	2651	1			T8	1		T13	12		T34	4
valid_sources[0x7e]	2287	1			T6	1		T8	2		T13	20
valid_sources[0x7f]	2396	1			T13	14		T21	1		T34	1
valid_sources[0x80]	3711	1			T6	1		T8	1		T13	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

100210

1

T2

1

T3

4

T4

13

values[0x0]

all_enables

biggest_size

62950

1

T3

1

T4

1

T5

5

values[0x1]

all_enables

biggest_size

33919

1

T3

1

T4

1

T5

3