SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35273 | 1 | T21 | 292 | T22 | 282 | T35 | 316 | ||||
others[1] | 34854 | 1 | T13 | 1 | T21 | 309 | T22 | 310 | ||||
others[2] | 34863 | 1 | T21 | 312 | T22 | 300 | T35 | 318 | ||||
others[3] | 58491 | 1 | T13 | 1 | T21 | 490 | T22 | 507 | ||||
false | 18870 | 1 | T5 | 2 | T8 | 32 | T13 | 111 | ||||
true | 28770 | 1 | T1 | 3 | T2 | 5 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35121 | 1 | T21 | 295 | T22 | 304 | T35 | 283 | ||||
others[1] | 34723 | 1 | T21 | 299 | T22 | 298 | T35 | 319 | ||||
others[2] | 35445 | 1 | T13 | 1 | T21 | 314 | T22 | 293 | ||||
others[3] | 58366 | 1 | T21 | 496 | T22 | 512 | T35 | 514 | ||||
false | 12033 | 1 | T5 | 2 | T8 | 16 | T13 | 58 | ||||
true | 21988 | 1 | T1 | 3 | T2 | 5 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 658 | 1 | T13 | 2 | T34 | 2 | T14 | 5 | ||||
others[1] | 660 | 1 | T5 | 1 | T13 | 4 | T34 | 1 | ||||
others[2] | 663 | 1 | T10 | 1 | T13 | 8 | T14 | 9 | ||||
others[3] | 1087 | 1 | T5 | 1 | T10 | 4 | T13 | 9 | ||||
false | 13142 | 1 | T1 | 3 | T2 | 5 | T3 | 1 | ||||
true | 3822 | 1 | T5 | 2 | T10 | 4 | T13 | 45 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |