Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T8
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T13,T22

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	24433688	6153	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	24433688	263501	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	24433688	10202754	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	24433688	263487	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	24433688	6153	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	24433688	263501	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	24433688	10202754	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	24433688	263487	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	6153	0	0
T4	1664	2	0	0
T5	4201	0	0	0
T6	8146	0	0	0
T7	1388	0	0	0
T8	8061	6	0	0
T9	694	0	0	0
T10	5570	0	0	0
T13	99184	27	0	0
T14	0	84	0	0
T21	0	19	0	0
T22	0	26	0	0
T35	0	29	0	0
T36	4967	0	0	0
T37	1521	0	0	0
T38	0	1	0	0
T41	0	3	0	0
T77	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	263501	0	0
T4	1664	175	0	0
T5	4201	0	0	0
T6	8146	0	0	0
T7	1388	0	0	0
T8	8061	139	0	0
T9	694	0	0	0
T10	5570	0	0	0
T13	99184	546	0	0
T14	0	2056	0	0
T21	0	834	0	0
T22	0	1847	0	0
T35	0	578	0	0
T36	4967	0	0	0
T37	1521	0	0	0
T38	0	10	0	0
T41	0	232	0	0
T77	0	13	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	10202754	0	0
T4	1664	107	0	0
T5	4201	0	0	0
T6	8146	6405	0	0
T7	1388	0	0	0
T8	8061	3624	0	0
T9	694	0	0	0
T10	5570	0	0	0
T13	99184	39681	0	0
T21	0	18008	0	0
T22	0	31783	0	0
T36	4967	2328	0	0
T37	1521	0	0	0
T38	0	951	0	0
T57	0	2118	0	0
T77	0	864	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	263487	0	0
T4	1664	175	0	0
T5	4201	0	0	0
T6	8146	0	0	0
T7	1388	0	0	0
T8	8061	139	0	0
T9	694	0	0	0
T10	5570	0	0	0
T13	99184	546	0	0
T14	0	2048	0	0
T21	0	834	0	0
T22	0	1847	0	0
T35	0	578	0	0
T36	4967	0	0	0
T37	1521	0	0	0
T38	0	10	0	0
T41	0	232	0	0
T77	0	13	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	6153	0	0
T4	1664	2	0	0
T5	4201	0	0	0
T6	8146	0	0	0
T7	1388	0	0	0
T8	8061	6	0	0
T9	694	0	0	0
T10	5570	0	0	0
T13	99184	27	0	0
T14	0	84	0	0
T21	0	19	0	0
T22	0	26	0	0
T35	0	29	0	0
T36	4967	0	0	0
T37	1521	0	0	0
T38	0	1	0	0
T41	0	3	0	0
T77	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	263501	0	0
T4	1664	175	0	0
T5	4201	0	0	0
T6	8146	0	0	0
T7	1388	0	0	0
T8	8061	139	0	0
T9	694	0	0	0
T10	5570	0	0	0
T13	99184	546	0	0
T14	0	2056	0	0
T21	0	834	0	0
T22	0	1847	0	0
T35	0	578	0	0
T36	4967	0	0	0
T37	1521	0	0	0
T38	0	10	0	0
T41	0	232	0	0
T77	0	13	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	10202754	0	0
T4	1664	107	0	0
T5	4201	0	0	0
T6	8146	6405	0	0
T7	1388	0	0	0
T8	8061	3624	0	0
T9	694	0	0	0
T10	5570	0	0	0
T13	99184	39681	0	0
T21	0	18008	0	0
T22	0	31783	0	0
T36	4967	2328	0	0
T37	1521	0	0	0
T38	0	951	0	0
T57	0	2118	0	0
T77	0	864	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	263487	0	0
T4	1664	175	0	0
T5	4201	0	0	0
T6	8146	0	0	0
T7	1388	0	0	0
T8	8061	139	0	0
T9	694	0	0	0
T10	5570	0	0	0
T13	99184	546	0	0
T14	0	2048	0	0
T21	0	834	0	0
T22	0	1847	0	0
T35	0	578	0	0
T36	4967	0	0	0
T37	1521	0	0	0
T38	0	10	0	0
T41	0	232	0	0
T77	0	13	0	0