Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25043944	13950	0	0
intr_enable_rd_A	25043944	50935	0	0
reset_en_rd_A	25043944	1625	0	0
reset_en_regwen_rd_A	25043944	1382	0	0
wake_info_capture_dis_rd_A	25043944	1399	0	0
wakeup_en_rd_A	25043944	2743	0	0
wakeup_en_regwen_rd_A	25043944	1509	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25043944	13950	0	0
T11	15756	0	0	0
T13	99184	1	0	0
T14	0	1	0	0
T20	0	1	0	0
T21	41217	0	0	0
T22	55483	0	0	0
T34	7630	0	0	0
T36	4967	0	0	0
T37	1521	0	0	0
T38	1275	0	0	0
T46	0	15	0	0
T47	0	80	0	0
T51	0	31	0	0
T57	4604	0	0	0
T77	1124	0	0	0
T87	0	10	0	0
T141	0	5	0	0
T142	0	32	0	0
T143	0	27	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25043944	50935	0	0
T3	1552	6	0	0
T4	1664	0	0	0
T5	4201	0	0	0
T6	8146	0	0	0
T7	1388	0	0	0
T8	8061	46	0	0
T9	694	0	0	0
T10	5570	0	0	0
T13	99184	877	0	0
T14	0	2583	0	0
T21	0	141	0	0
T36	4967	0	0	0
T38	0	4	0	0
T80	0	116	0	0
T100	0	16	0	0
T144	0	25	0	0
T145	0	6	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25043944	1625	0	0
T11	15756	0	0	0
T13	99184	8	0	0
T20	0	9	0	0
T21	41217	0	0	0
T22	55483	0	0	0
T34	7630	0	0	0
T36	4967	0	0	0
T37	1521	0	0	0
T38	1275	0	0	0
T51	0	16	0	0
T57	4604	0	0	0
T77	1124	0	0	0
T81	0	3	0	0
T83	0	2	0	0
T95	0	5	0	0
T146	0	14	0	0
T147	0	14	0	0
T148	0	6	0	0
T149	0	4	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25043944	1382	0	0
T20	79317	5	0	0
T51	0	20	0	0
T95	0	13	0	0
T136	1754	0	0	0
T137	11338	0	0	0
T146	0	10	0	0
T147	0	15	0	0
T148	0	7	0	0
T149	0	7	0	0
T150	0	7	0	0
T151	0	8	0	0
T152	0	7	0	0
T153	2075	0	0	0
T154	28273	0	0	0
T155	3919	0	0	0
T156	15614	0	0	0
T157	5192	0	0	0
T158	1709	0	0	0
T159	4604	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25043944	1399	0	0
T11	15756	0	0	0
T13	99184	1	0	0
T20	0	2	0	0
T21	41217	0	0	0
T22	55483	0	0	0
T34	7630	0	0	0
T36	4967	0	0	0
T37	1521	0	0	0
T38	1275	0	0	0
T51	0	16	0	0
T57	4604	0	0	0
T77	1124	0	0	0
T81	0	12	0	0
T95	0	6	0	0
T146	0	11	0	0
T147	0	1	0	0
T148	0	8	0	0
T149	0	6	0	0
T150	0	4	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25043944	2743	0	0
T20	79317	4	0	0
T51	0	15	0	0
T81	0	6	0	0
T95	0	9	0	0
T136	1754	0	0	0
T137	11338	0	0	0
T146	0	15	0	0
T147	0	14	0	0
T148	0	3	0	0
T149	0	4	0	0
T152	0	13	0	0
T153	2075	0	0	0
T154	28273	0	0	0
T155	3919	0	0	0
T156	15614	0	0	0
T157	5192	0	0	0
T158	1709	0	0	0
T159	4604	0	0	0
T160	0	3	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25043944	1509	0	0
T11	15756	0	0	0
T13	99184	6	0	0
T20	0	4	0	0
T21	41217	0	0	0
T22	55483	0	0	0
T34	7630	0	0	0
T36	4967	0	0	0
T37	1521	0	0	0
T38	1275	0	0	0
T51	0	31	0	0
T57	4604	0	0	0
T77	1124	0	0	0
T95	0	16	0	0
T146	0	8	0	0
T147	0	10	0	0
T148	0	10	0	0
T149	0	2	0	0
T150	0	10	0	0
T160	0	3	0	0