Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	73301064	144432	0	0
StatusRise_A	73301064	160879	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73301064	144432	0	0
T3	4656	3	0	0
T4	4992	12	0	0
T5	12603	18	0	0
T6	24438	22	0	0
T7	4164	0	0	0
T8	24183	72	0	0
T9	2082	3	0	0
T10	16710	42	0	0
T13	297552	1152	0	0
T36	14901	49	0	0
T38	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73301064	160879	0	0
T1	3300	9	0	0
T2	10428	15	0	0
T3	4656	6	0	0
T4	4992	15	0	0
T5	12603	21	0	0
T6	24438	24	0	0
T7	4164	21	0	0
T8	24183	74	0	0
T9	2082	9	0	0
T10	16710	45	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24433688	53684	0	0
StatusRise_A	24433688	59646	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	53684	0	0
T3	1552	1	0	0
T4	1664	4	0	0
T5	4201	6	0	0
T6	8146	8	0	0
T7	1388	0	0	0
T8	8061	28	0	0
T9	694	1	0	0
T10	5570	14	0	0
T13	99184	411	0	0
T36	4967	20	0	0
T38	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	59646	0	0
T1	1100	3	0	0
T2	3476	5	0	0
T3	1552	2	0	0
T4	1664	5	0	0
T5	4201	7	0	0
T6	8146	9	0	0
T7	1388	7	0	0
T8	8061	29	0	0
T9	694	3	0	0
T10	5570	15	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24433688	53684	0	0
StatusRise_A	24433688	59647	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	53684	0	0
T3	1552	1	0	0
T4	1664	4	0	0
T5	4201	6	0	0
T6	8146	8	0	0
T7	1388	0	0	0
T8	8061	28	0	0
T9	694	1	0	0
T10	5570	14	0	0
T13	99184	411	0	0
T36	4967	20	0	0
T38	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	59647	0	0
T1	1100	3	0	0
T2	3476	5	0	0
T3	1552	2	0	0
T4	1664	5	0	0
T5	4201	7	0	0
T6	8146	9	0	0
T7	1388	7	0	0
T8	8061	29	0	0
T9	694	3	0	0
T10	5570	15	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24433688	37064	0	0
StatusRise_A	24433688	41586	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	37064	0	0
T3	1552	1	0	0
T4	1664	4	0	0
T5	4201	6	0	0
T6	8146	6	0	0
T7	1388	0	0	0
T8	8061	16	0	0
T9	694	1	0	0
T10	5570	14	0	0
T13	99184	330	0	0
T36	4967	9	0	0
T38	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	41586	0	0
T1	1100	3	0	0
T2	3476	5	0	0
T3	1552	2	0	0
T4	1664	5	0	0
T5	4201	7	0	0
T6	8146	6	0	0
T7	1388	7	0	0
T8	8061	16	0	0
T9	694	3	0	0
T10	5570	15	0	0