Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	24434281	6300	0	0
EscTimeoutStoppedByClReset_A	24433688	3395629	0	0
EscTimeoutTriggersReset_A	4758128	321	0	0
RomAllowActiveState_A	24433688	59270	0	0
RomAllowCheckGoodState_A	24433688	59320	0	0
RomBlockActiveState_A	24433688	28239	0	0
RomBlockCheckGoodState_A	24433688	416281	0	0
RomIntgChkDisFalse_A	24433688	23801060	0	0
RomIntgChkDisTrue_A	24433688	120989	0	0
RstreqChkEsctimeout_A	24433688	4123	0	0
RstreqChkFsmterm_A	24433688	140	0	0
RstreqChkGlbesc_A	24433688	4123	0	0
RstreqChkMainpd_A	24433688	986782	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24434281	6300	0	0
T11	15757	163	0	0
T12	0	109	0	0
T14	281529	0	0	0
T16	1267	0	0	0
T22	55483	0	0	0
T35	15108	0	0	0
T41	1409	0	0	0
T44	3267	0	0	0
T57	4604	0	0	0
T61	3184	0	0	0
T77	1125	0	0	0
T101	0	62	0	0
T156	0	169	0	0
T161	0	21	0	0
T162	0	27	0	0
T163	0	129	0	0
T164	0	18	0	0
T165	0	8	0	0
T166	0	20	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	3395629	0	0
T1	1100	11	0	0
T2	3476	62	0	0
T3	1552	11	0	0
T4	1664	81	0	0
T5	4201	152	0	0
T6	8146	412	0	0
T7	1388	85	0	0
T8	8061	1009	0	0
T9	694	25	0	0
T10	5570	767	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4758128	321	0	0
T9	354	5	0	0
T10	420	0	0	0
T11	204	2	0	0
T12	0	3	0	0
T13	105685	0	0	0
T21	6090	0	0	0
T34	731	0	0	0
T36	3089	0	0	0
T37	523	0	0	0
T38	381	0	0	0
T57	461	0	0	0
T101	0	2	0	0
T156	0	2	0	0
T161	0	3	0	0
T162	0	2	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	59270	0	0
T1	1100	3	0	0
T2	3476	5	0	0
T3	1552	2	0	0
T4	1664	5	0	0
T5	4201	7	0	0
T6	8146	9	0	0
T7	1388	7	0	0
T8	8061	29	0	0
T9	694	3	0	0
T10	5570	15	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	59320	0	0
T1	1100	3	0	0
T2	3476	5	0	0
T3	1552	2	0	0
T4	1664	5	0	0
T5	4201	7	0	0
T6	8146	9	0	0
T7	1388	7	0	0
T8	8061	29	0	0
T9	694	3	0	0
T10	5570	15	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	28239	0	0
T5	4201	1024	0	0
T6	8146	0	0	0
T7	1388	0	0	0
T8	8061	0	0	0
T9	694	0	0	0
T10	5570	0	0	0
T13	99184	0	0	0
T35	0	10	0	0
T36	4967	0	0	0
T37	1521	0	0	0
T38	1275	0	0	0
T45	0	602	0	0
T80	0	4	0	0
T88	0	655	0	0
T167	0	153	0	0
T168	0	1	0	0
T169	0	1421	0	0
T170	0	13	0	0
T171	0	5	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	416281	0	0
T5	4201	403	0	0
T6	8146	0	0	0
T7	1388	0	0	0
T8	8061	366	0	0
T9	694	0	0	0
T10	5570	0	0	0
T13	99184	1282	0	0
T14	0	3166	0	0
T15	0	206	0	0
T21	0	2815	0	0
T22	0	4165	0	0
T35	0	1095	0	0
T36	4967	0	0	0
T37	1521	0	0	0
T38	1275	0	0	0
T78	0	412	0	0
T134	0	4092	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	23801060	0	0
T1	1100	902	0	0
T2	3476	3124	0	0
T3	1552	1484	0	0
T4	1664	1282	0	0
T5	4201	2303	0	0
T6	8146	8081	0	0
T7	1388	924	0	0
T8	8061	8004	0	0
T9	694	528	0	0
T10	5570	5517	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	120989	0	0
T5	4201	1833	0	0
T6	8146	0	0	0
T7	1388	0	0	0
T8	8061	0	0	0
T9	694	0	0	0
T10	5570	0	0	0
T13	99184	0	0	0
T21	0	863	0	0
T22	0	1734	0	0
T35	0	782	0	0
T36	4967	0	0	0
T37	1521	0	0	0
T38	1275	0	0	0
T45	0	580	0	0
T134	0	1886	0	0
T154	0	1325	0	0
T167	0	216	0	0
T172	0	8041	0	0
T173	0	1702	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	4123	0	0
T1	1100	2	0	0
T2	3476	0	0	0
T3	1552	0	0	0
T4	1664	0	0	0
T5	4201	2	0	0
T6	8146	0	0	0
T7	1388	0	0	0
T8	8061	0	0	0
T9	694	1	0	0
T10	5570	6	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	46	0	0
T14	0	68	0	0
T34	0	7	0	0
T37	0	4	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	140	0	0
T17	27395	40	0	0
T18	0	20	0	0
T19	0	20	0	0
T23	0	40	0	0
T24	0	20	0	0
T25	111017	0	0	0
T26	26796	0	0	0
T27	3732	0	0	0
T28	2117	0	0	0
T29	1362	0	0	0
T30	3899	0	0	0
T31	14656	0	0	0
T32	28202	0	0	0
T33	5829	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	4123	0	0
T1	1100	2	0	0
T2	3476	0	0	0
T3	1552	0	0	0
T4	1664	0	0	0
T5	4201	2	0	0
T6	8146	0	0	0
T7	1388	0	0	0
T8	8061	0	0	0
T9	694	1	0	0
T10	5570	6	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	46	0	0
T14	0	68	0	0
T34	0	7	0	0
T37	0	4	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24433688	986782	0	0
T2	3476	16	0	0
T3	1552	0	0	0
T4	1664	0	0	0
T5	4201	658	0	0
T6	8146	0	0	0
T7	1388	27	0	0
T8	8061	534	0	0
T9	694	0	0	0
T10	5570	699	0	0
T13	99184	1772	0	0
T16	0	5	0	0
T21	0	3378	0	0
T22	0	7365	0	0
T34	0	215	0	0