Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	513216	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

196036

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	372231	1			T1	1		T2	1		T3	1
values[0x0]	168174	1			T4	10		T5	237		T6	36
values[0x1]	168847	1			T4	6		T5	215		T6	26

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	406381	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

302871

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3284	1			T12	4		T16	34		T17	1
valid_sources[0x01]	2776	1			T5	1		T6	1		T10	1
valid_sources[0x02]	2831	1			T5	3		T13	59		T55	1
valid_sources[0x03]	3410	1			T5	8		T12	23		T27	2
valid_sources[0x04]	2626	1			T5	9		T6	1		T7	7
valid_sources[0x05]	3509	1			T5	1		T15	35		T55	1
valid_sources[0x06]	3082	1			T5	12		T6	1		T45	3
valid_sources[0x07]	4585	1			T5	3		T7	2		T12	1
valid_sources[0x08]	2476	1			T5	9		T6	1		T7	1
valid_sources[0x09]	2316	1			T5	2		T6	1		T9	21
valid_sources[0x0a]	5405	1			T5	1		T6	5		T10	3
valid_sources[0x0b]	2116	1			T5	1		T6	1		T7	6
valid_sources[0x0c]	2630	1			T5	2		T7	6		T15	30
valid_sources[0x0d]	2210	1			T6	1		T12	6		T45	1
valid_sources[0x0e]	2597	1			T5	9		T10	3		T45	1
valid_sources[0x0f]	3891	1			T5	2		T6	1		T7	20
valid_sources[0x10]	2317	1			T5	1		T6	1		T7	3
valid_sources[0x11]	2193	1			T5	1		T10	4		T45	1
valid_sources[0x12]	3278	1			T5	1		T15	15		T16	27
valid_sources[0x13]	2992	1			T5	3		T6	1		T7	2
valid_sources[0x14]	2273	1			T45	1		T55	2		T27	1
valid_sources[0x15]	2245	1			T5	5		T6	3		T27	3
valid_sources[0x16]	2212	1			T5	4		T54	3		T27	3
valid_sources[0x17]	3394	1			T5	4		T6	1		T55	1
valid_sources[0x18]	2373	1			T6	2		T10	1		T12	8
valid_sources[0x19]	2266	1			T6	1		T27	2		T16	25
valid_sources[0x1a]	2154	1			T5	1		T6	2		T40	1
valid_sources[0x1b]	3363	1			T11	34		T27	4		T16	16
valid_sources[0x1c]	2231	1			T5	3		T8	1		T12	8
valid_sources[0x1d]	2227	1			T5	1		T6	3		T54	6
valid_sources[0x1e]	2075	1			T5	6		T6	1		T7	1
valid_sources[0x1f]	2204	1			T5	3		T6	4		T15	14
valid_sources[0x20]	2237	1			T5	13		T12	27		T45	1
valid_sources[0x21]	3089	1			T5	2		T6	1		T7	11
valid_sources[0x22]	2619	1			T10	1		T12	14		T45	4
valid_sources[0x23]	3061	1			T5	2		T6	1		T26	1
valid_sources[0x24]	2076	1			T5	6		T6	1		T7	3
valid_sources[0x25]	2165	1			T5	1		T6	1		T7	6
valid_sources[0x26]	2993	1			T5	1		T7	2		T14	2
valid_sources[0x27]	2356	1			T5	1		T6	1		T45	2
valid_sources[0x28]	2987	1			T5	8		T6	2		T45	1
valid_sources[0x29]	2187	1			T1	1		T5	5		T7	3
valid_sources[0x2a]	2176	1			T5	10		T10	1		T45	1
valid_sources[0x2b]	2409	1			T5	5		T6	1		T7	4
valid_sources[0x2c]	2663	1			T5	2		T6	2		T10	1
valid_sources[0x2d]	3005	1			T5	6		T7	5		T55	1
valid_sources[0x2e]	2172	1			T5	2		T15	35		T27	8
valid_sources[0x2f]	2062	1			T5	2		T12	4		T27	5
valid_sources[0x30]	2108	1			T5	2		T27	11		T16	27
valid_sources[0x31]	2480	1			T5	9		T6	1		T10	1
valid_sources[0x32]	3067	1			T5	5		T6	2		T10	2
valid_sources[0x33]	2377	1			T6	1		T7	3		T10	1
valid_sources[0x34]	2070	1			T45	2		T27	5		T16	25
valid_sources[0x35]	2090	1			T5	11		T6	1		T45	5
valid_sources[0x36]	2187	1			T5	1		T16	31		T17	12
valid_sources[0x37]	3053	1			T5	1		T16	36		T17	4
valid_sources[0x38]	2145	1			T5	4		T10	2		T12	3
valid_sources[0x39]	2127	1			T5	4		T7	3		T15	25
valid_sources[0x3a]	2330	1			T5	6		T9	9		T16	19
valid_sources[0x3b]	3365	1			T10	2		T12	2		T45	1
valid_sources[0x3c]	2038	1			T5	11		T10	1		T45	1
valid_sources[0x3d]	2214	1			T5	6		T10	3		T54	3
valid_sources[0x3e]	2485	1			T5	1		T6	1		T10	1
valid_sources[0x3f]	4439	1			T15	19		T27	4		T16	62
valid_sources[0x40]	2022	1			T5	4		T6	3		T12	1
valid_sources[0x41]	2149	1			T5	1		T6	1		T12	7
valid_sources[0x42]	2878	1			T5	3		T7	1		T10	2
valid_sources[0x43]	2069	1			T5	6		T6	1		T7	2
valid_sources[0x44]	6624	1			T5	7		T6	3		T14	1
valid_sources[0x45]	1950	1			T5	1		T6	1		T12	6
valid_sources[0x46]	2597	1			T5	6		T6	2		T45	2
valid_sources[0x47]	2310	1			T5	11		T45	2		T27	3
valid_sources[0x48]	2333	1			T5	2		T6	3		T15	9
valid_sources[0x49]	2221	1			T5	3		T6	3		T7	7
valid_sources[0x4a]	2178	1			T45	1		T14	1		T15	37
valid_sources[0x4b]	4132	1			T5	4		T6	3		T12	3
valid_sources[0x4c]	3712	1			T5	4		T12	16		T15	40
valid_sources[0x4d]	2133	1			T5	3		T6	1		T45	3
valid_sources[0x4e]	2604	1			T5	1		T10	1		T45	6
valid_sources[0x4f]	2074	1			T5	4		T12	23		T45	4
valid_sources[0x50]	2096	1			T6	3		T27	4		T16	27
valid_sources[0x51]	1917	1			T5	5		T6	2		T45	3
valid_sources[0x52]	2041	1			T5	6		T14	1		T27	6
valid_sources[0x53]	4170	1			T5	1		T6	1		T7	2
valid_sources[0x54]	4013	1			T5	2		T6	1		T45	4
valid_sources[0x55]	2072	1			T10	1		T12	6		T27	7
valid_sources[0x56]	3342	1			T5	7		T6	3		T7	3
valid_sources[0x57]	2244	1			T5	4		T7	2		T45	2
valid_sources[0x58]	3908	1			T5	7		T6	2		T45	3
valid_sources[0x59]	2206	1			T5	3		T12	13		T45	3
valid_sources[0x5a]	4280	1			T7	2		T10	1		T45	3
valid_sources[0x5b]	2253	1			T5	5		T6	1		T45	1
valid_sources[0x5c]	3389	1			T5	10		T10	1		T45	1
valid_sources[0x5d]	2094	1			T5	5		T12	19		T45	2
valid_sources[0x5e]	1985	1			T5	5		T6	2		T7	5
valid_sources[0x5f]	2470	1			T5	6		T10	2		T12	1
valid_sources[0x60]	2164	1			T5	1		T7	2		T27	7
valid_sources[0x61]	2602	1			T5	9		T12	5		T15	15
valid_sources[0x62]	2160	1			T12	6		T45	2		T16	37
valid_sources[0x63]	2126	1			T5	3		T6	2		T16	34
valid_sources[0x64]	2092	1			T5	1		T6	1		T10	1
valid_sources[0x65]	3208	1			T5	1		T16	28		T17	10
valid_sources[0x66]	2714	1			T6	2		T7	1		T10	1
valid_sources[0x67]	2496	1			T5	2		T45	1		T54	3
valid_sources[0x68]	2161	1			T7	3		T12	1		T14	2
valid_sources[0x69]	11118	1			T5	7		T6	1		T27	14
valid_sources[0x6a]	2192	1			T5	5		T45	2		T27	4
valid_sources[0x6b]	2349	1			T5	13		T6	2		T7	1
valid_sources[0x6c]	2299	1			T5	2		T12	12		T45	1
valid_sources[0x6d]	5875	1			T5	6		T45	3		T14	1
valid_sources[0x6e]	2636	1			T5	6		T12	15		T45	1
valid_sources[0x6f]	2350	1			T14	1		T27	8		T16	43
valid_sources[0x70]	8872	1			T5	1		T6	1		T16	30
valid_sources[0x71]	2671	1			T5	1		T12	7		T15	2
valid_sources[0x72]	4403	1			T16	47		T17	2		T43	1
valid_sources[0x73]	3506	1			T5	2		T6	1		T12	9
valid_sources[0x74]	2154	1			T5	2		T6	1		T7	3
valid_sources[0x75]	2089	1			T5	3		T6	1		T7	3
valid_sources[0x76]	5970	1			T5	4		T6	3		T10	1
valid_sources[0x77]	1980	1			T5	2		T10	1		T45	1
valid_sources[0x78]	3021	1			T5	3		T6	2		T45	2
valid_sources[0x79]	2458	1			T5	1		T6	2		T12	11
valid_sources[0x7a]	2945	1			T5	6		T10	1		T12	1
valid_sources[0x7b]	1915	1			T5	4		T6	4		T10	2
valid_sources[0x7c]	2210	1			T5	2		T6	1		T27	2
valid_sources[0x7d]	2376	1			T5	4		T6	2		T45	2
valid_sources[0x7e]	3037	1			T5	3		T6	3		T7	4
valid_sources[0x7f]	2247	1			T5	4		T6	1		T12	5
valid_sources[0x80]	2887	1			T5	2		T6	2		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

99821

1

T1

1

T2

1

T3

1

values[0x0]

all_enables

biggest_size

62255

1

T4

4

T5

73

T6

14

values[0x1]

all_enables

biggest_size

33960

1

T5

32

T6

3

T7

8