SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34959 | 1 | T5 | 391 | T12 | 317 | T27 | 293 | ||||
others[1] | 35011 | 1 | T5 | 389 | T12 | 287 | T27 | 306 | ||||
others[2] | 35185 | 1 | T5 | 415 | T12 | 304 | T27 | 294 | ||||
others[3] | 58226 | 1 | T5 | 667 | T12 | 490 | T14 | 1 | ||||
false | 18317 | 1 | T5 | 50 | T12 | 50 | T14 | 2 | ||||
true | 28316 | 1 | T1 | 2 | T2 | 2 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34801 | 1 | T5 | 429 | T12 | 317 | T27 | 286 | ||||
others[1] | 35179 | 1 | T5 | 381 | T12 | 298 | T27 | 296 | ||||
others[2] | 35277 | 1 | T5 | 382 | T12 | 310 | T14 | 1 | ||||
others[3] | 58310 | 1 | T5 | 676 | T12 | 477 | T27 | 525 | ||||
false | 11771 | 1 | T5 | 50 | T12 | 50 | T14 | 4 | ||||
true | 21830 | 1 | T1 | 2 | T2 | 2 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 683 | 1 | T6 | 5 | T7 | 9 | T10 | 3 | ||||
others[1] | 663 | 1 | T6 | 9 | T7 | 3 | T13 | 1 | ||||
others[2] | 689 | 1 | T6 | 5 | T7 | 8 | T45 | 5 | ||||
others[3] | 1200 | 1 | T6 | 6 | T7 | 4 | T10 | 1 | ||||
false | 13725 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | ||||
true | 4115 | 1 | T6 | 2 | T7 | 1 | T10 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |