Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T9,T27

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	25088886	6074	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	25088886	265432	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	25088886	10452526	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	25088886	265379	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	25088886	6074	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	25088886	265432	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	25088886	10452526	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	25088886	265379	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	6074	0	0
T4	1603	1	0	0
T5	23389	24	0	0
T6	4339	0	0	0
T7	4981	0	0	0
T8	15524	0	0	0
T9	3286	3	0	0
T10	2283	0	0	0
T11	2872	0	0	0
T12	0	20	0	0
T13	3317	0	0	0
T15	0	1	0	0
T16	0	51	0	0
T17	0	5	0	0
T24	0	62	0	0
T26	2168	0	0	0
T27	0	23	0	0
T77	0	13	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	265432	0	0
T4	1603	75	0	0
T5	23389	517	0	0
T6	4339	0	0	0
T7	4981	0	0	0
T8	15524	0	0	0
T9	3286	729	0	0
T10	2283	0	0	0
T11	2872	0	0	0
T12	0	419	0	0
T13	3317	0	0	0
T15	0	15	0	0
T16	0	1432	0	0
T17	0	90	0	0
T24	0	2296	0	0
T26	2168	0	0	0
T27	0	1424	0	0
T77	0	760	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	10452526	0	0
T4	1603	739	0	0
T5	23389	12163	0	0
T6	4339	0	0	0
T7	4981	0	0	0
T8	15524	0	0	0
T9	3286	1049	0	0
T10	2283	0	0	0
T11	2872	1369	0	0
T12	0	10130	0	0
T13	3317	0	0	0
T15	0	5950	0	0
T26	2168	0	0	0
T27	0	29385	0	0
T54	0	518	0	0
T55	0	1100	0	0
T59	0	8081	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	265379	0	0
T4	1603	75	0	0
T5	23389	517	0	0
T6	4339	0	0	0
T7	4981	0	0	0
T8	15524	0	0	0
T9	3286	729	0	0
T10	2283	0	0	0
T11	2872	0	0	0
T12	0	419	0	0
T13	3317	0	0	0
T15	0	15	0	0
T16	0	1432	0	0
T17	0	90	0	0
T24	0	2292	0	0
T26	2168	0	0	0
T27	0	1424	0	0
T77	0	760	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	6074	0	0
T4	1603	1	0	0
T5	23389	24	0	0
T6	4339	0	0	0
T7	4981	0	0	0
T8	15524	0	0	0
T9	3286	3	0	0
T10	2283	0	0	0
T11	2872	0	0	0
T12	0	20	0	0
T13	3317	0	0	0
T15	0	1	0	0
T16	0	51	0	0
T17	0	5	0	0
T24	0	62	0	0
T26	2168	0	0	0
T27	0	23	0	0
T77	0	13	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	265432	0	0
T4	1603	75	0	0
T5	23389	517	0	0
T6	4339	0	0	0
T7	4981	0	0	0
T8	15524	0	0	0
T9	3286	729	0	0
T10	2283	0	0	0
T11	2872	0	0	0
T12	0	419	0	0
T13	3317	0	0	0
T15	0	15	0	0
T16	0	1432	0	0
T17	0	90	0	0
T24	0	2296	0	0
T26	2168	0	0	0
T27	0	1424	0	0
T77	0	760	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	10452526	0	0
T4	1603	739	0	0
T5	23389	12163	0	0
T6	4339	0	0	0
T7	4981	0	0	0
T8	15524	0	0	0
T9	3286	1049	0	0
T10	2283	0	0	0
T11	2872	1369	0	0
T12	0	10130	0	0
T13	3317	0	0	0
T15	0	5950	0	0
T26	2168	0	0	0
T27	0	29385	0	0
T54	0	518	0	0
T55	0	1100	0	0
T59	0	8081	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	265379	0	0
T4	1603	75	0	0
T5	23389	517	0	0
T6	4339	0	0	0
T7	4981	0	0	0
T8	15524	0	0	0
T9	3286	729	0	0
T10	2283	0	0	0
T11	2872	0	0	0
T12	0	419	0	0
T13	3317	0	0	0
T15	0	15	0	0
T16	0	1432	0	0
T17	0	90	0	0
T24	0	2292	0	0
T26	2168	0	0	0
T27	0	1424	0	0
T77	0	760	0	0