Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25624752	13550	0	0
intr_enable_rd_A	25624752	38418	0	0
reset_en_rd_A	25624752	1359	0	0
reset_en_regwen_rd_A	25624752	1185	0	0
wake_info_capture_dis_rd_A	25624752	1135	0	0
wakeup_en_rd_A	25624752	2483	0	0
wakeup_en_regwen_rd_A	25624752	1147	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25624752	13550	0	0
T16	205235	5	0	0
T17	58298	0	0	0
T21	43465	0	0	0
T24	0	22	0	0
T25	0	20	0	0
T38	3155	0	0	0
T42	7353	0	0	0
T43	2473	0	0	0
T44	1153	0	0	0
T50	0	15	0	0
T77	52327	0	0	0
T108	0	10	0	0
T149	1695	0	0	0
T151	0	5	0	0
T152	0	21	0	0
T153	0	1	0	0
T154	0	5	0	0
T155	0	18	0	0
T156	1065	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25624752	38418	0	0
T12	22546	94	0	0
T14	1903	0	0	0
T15	19643	0	0	0
T17	0	521	0	0
T27	57398	93	0	0
T37	0	393	0	0
T39	2451	0	0	0
T40	15089	0	0	0
T41	15623	0	0	0
T45	2884	0	0	0
T54	4001	16	0	0
T55	1588	8	0	0
T79	0	24	0	0
T97	0	7	0	0
T102	0	57	0	0
T157	0	69	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25624752	1359	0	0
T20	3674	0	0	0
T47	0	47	0	0
T48	0	39	0	0
T49	0	11	0	0
T50	0	12	0	0
T51	0	14	0	0
T81	0	5	0	0
T127	1873	0	0	0
T154	285617	6	0	0
T155	0	3	0	0
T158	0	4	0	0
T159	0	10	0	0
T160	5741	0	0	0
T161	1651	0	0	0
T162	1206	0	0	0
T163	7084	0	0	0
T164	15256	0	0	0
T165	2595	0	0	0
T166	38441	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25624752	1185	0	0
T20	3674	0	0	0
T47	0	34	0	0
T48	0	12	0	0
T50	0	10	0	0
T51	0	7	0	0
T81	0	8	0	0
T127	1873	0	0	0
T154	285617	15	0	0
T155	0	14	0	0
T158	0	8	0	0
T160	5741	0	0	0
T161	1651	0	0	0
T162	1206	0	0	0
T163	7084	0	0	0
T164	15256	0	0	0
T165	2595	0	0	0
T166	38441	0	0	0
T167	0	14	0	0
T168	0	5	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25624752	1135	0	0
T20	3674	0	0	0
T47	0	32	0	0
T50	0	25	0	0
T51	0	12	0	0
T81	0	6	0	0
T127	1873	0	0	0
T154	285617	9	0	0
T155	0	11	0	0
T158	0	2	0	0
T160	5741	0	0	0
T161	1651	0	0	0
T162	1206	0	0	0
T163	7084	0	0	0
T164	15256	0	0	0
T165	2595	0	0	0
T166	38441	0	0	0
T167	0	5	0	0
T169	0	4	0	0
T170	0	3	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25624752	2483	0	0
T20	3674	0	0	0
T47	0	100	0	0
T50	0	16	0	0
T51	0	4	0	0
T81	0	7	0	0
T127	1873	0	0	0
T154	285617	21	0	0
T155	0	17	0	0
T158	0	3	0	0
T160	5741	0	0	0
T161	1651	0	0	0
T162	1206	0	0	0
T163	7084	0	0	0
T164	15256	0	0	0
T165	2595	0	0	0
T166	38441	0	0	0
T167	0	4	0	0
T168	0	5	0	0
T169	0	3	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25624752	1147	0	0
T20	3674	0	0	0
T47	0	30	0	0
T48	0	30	0	0
T50	0	6	0	0
T51	0	5	0	0
T81	0	3	0	0
T127	1873	0	0	0
T154	285617	3	0	0
T155	0	14	0	0
T158	0	3	0	0
T160	5741	0	0	0
T161	1651	0	0	0
T162	1206	0	0	0
T163	7084	0	0	0
T164	15256	0	0	0
T165	2595	0	0	0
T166	38441	0	0	0
T167	0	1	0	0
T169	0	14	0	0