Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	75266658	145333	0	0
StatusRise_A	75266658	162226	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75266658	145333	0	0
T1	2067	3	0	0
T2	6948	3	0	0
T3	4035	3	0	0
T4	4809	12	0	0
T5	70167	227	0	0
T6	13017	6	0	0
T7	14943	3	0	0
T8	46572	15	0	0
T9	9858	12	0	0
T10	6849	33	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75266658	162226	0	0
T1	2067	9	0	0
T2	6948	9	0	0
T3	4035	9	0	0
T4	4809	15	0	0
T5	70167	230	0	0
T6	13017	9	0	0
T7	14943	6	0	0
T8	46572	18	0	0
T9	9858	15	0	0
T10	6849	36	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25088886	53882	0	0
StatusRise_A	25088886	59989	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	53882	0	0
T1	689	1	0	0
T2	2316	1	0	0
T3	1345	1	0	0
T4	1603	4	0	0
T5	23389	90	0	0
T6	4339	2	0	0
T7	4981	1	0	0
T8	15524	5	0	0
T9	3286	4	0	0
T10	2283	11	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	59989	0	0
T1	689	3	0	0
T2	2316	3	0	0
T3	1345	3	0	0
T4	1603	5	0	0
T5	23389	91	0	0
T6	4339	3	0	0
T7	4981	2	0	0
T8	15524	6	0	0
T9	3286	5	0	0
T10	2283	12	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25088886	53882	0	0
StatusRise_A	25088886	59990	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	53882	0	0
T1	689	1	0	0
T2	2316	1	0	0
T3	1345	1	0	0
T4	1603	4	0	0
T5	23389	90	0	0
T6	4339	2	0	0
T7	4981	1	0	0
T8	15524	5	0	0
T9	3286	4	0	0
T10	2283	11	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	59990	0	0
T1	689	3	0	0
T2	2316	3	0	0
T3	1345	3	0	0
T4	1603	5	0	0
T5	23389	91	0	0
T6	4339	3	0	0
T7	4981	2	0	0
T8	15524	6	0	0
T9	3286	5	0	0
T10	2283	12	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	25088886	37569	0	0
StatusRise_A	25088886	42247	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	37569	0	0
T1	689	1	0	0
T2	2316	1	0	0
T3	1345	1	0	0
T4	1603	4	0	0
T5	23389	47	0	0
T6	4339	2	0	0
T7	4981	1	0	0
T8	15524	5	0	0
T9	3286	4	0	0
T10	2283	11	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	42247	0	0
T1	689	3	0	0
T2	2316	3	0	0
T3	1345	3	0	0
T4	1603	5	0	0
T5	23389	48	0	0
T6	4339	3	0	0
T7	4981	2	0	0
T8	15524	6	0	0
T9	3286	5	0	0
T10	2283	12	0	0