Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	25089511	6176	0	0
EscTimeoutStoppedByClReset_A	25088886	3540177	0	0
EscTimeoutTriggersReset_A	4998270	335	0	0
RomAllowActiveState_A	25088886	59602	0	0
RomAllowCheckGoodState_A	25088886	59652	0	0
RomBlockActiveState_A	25088886	25848	0	0
RomBlockCheckGoodState_A	25088886	437522	0	0
RomIntgChkDisFalse_A	25088886	24392267	0	0
RomIntgChkDisTrue_A	25088886	172162	0	0
RstreqChkEsctimeout_A	25088886	4442	0	0
RstreqChkFsmterm_A	25088886	160	0	0
RstreqChkGlbesc_A	25088886	4442	0	0
RstreqChkMainpd_A	25088886	1011936	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25089511	6176	0	0
T2	2317	28	0	0
T3	1346	0	0	0
T4	1604	0	0	0
T5	23390	0	0	0
T6	4339	0	0	0
T7	4981	0	0	0
T8	15525	130	0	0
T9	3287	0	0	0
T10	2284	0	0	0
T11	2872	0	0	0
T35	0	216	0	0
T40	0	122	0	0
T41	0	197	0	0
T171	0	271	0	0
T172	0	15	0	0
T173	0	5	0	0
T174	0	7	0	0
T175	0	263	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	3540177	0	0
T1	689	27	0	0
T2	2316	39	0	0
T3	1345	37	0	0
T4	1603	63	0	0
T5	23389	3236	0	0
T6	4339	26	0	0
T7	4981	11	0	0
T8	15524	80	0	0
T9	3286	45	0	0
T10	2283	190	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4998270	335	0	0
T1	335	6	0	0
T2	192	2	0	0
T3	219	3	0	0
T4	507	0	0	0
T5	8647	0	0	0
T6	678	0	0	0
T7	377	0	0	0
T8	201	2	0	0
T9	316	0	0	0
T10	1088	0	0	0
T35	0	3	0	0
T39	0	3	0	0
T40	0	3	0	0
T41	0	3	0	0
T156	0	4	0	0
T171	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	59602	0	0
T1	689	3	0	0
T2	2316	3	0	0
T3	1345	3	0	0
T4	1603	5	0	0
T5	23389	91	0	0
T6	4339	3	0	0
T7	4981	2	0	0
T8	15524	6	0	0
T9	3286	5	0	0
T10	2283	12	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	59652	0	0
T1	689	3	0	0
T2	2316	3	0	0
T3	1345	3	0	0
T4	1603	5	0	0
T5	23389	91	0	0
T6	4339	3	0	0
T7	4981	2	0	0
T8	15524	6	0	0
T9	3286	5	0	0
T10	2283	12	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	25848	0	0
T12	22546	14	0	0
T14	1903	250	0	0
T15	19643	0	0	0
T27	57398	0	0	0
T30	0	617	0	0
T33	0	744	0	0
T34	0	285	0	0
T38	0	524	0	0
T39	2451	0	0	0
T40	15089	0	0	0
T41	15623	0	0	0
T45	2884	0	0	0
T54	4001	0	0	0
T55	1588	0	0	0
T97	0	365	0	0
T176	0	306	0	0
T177	0	367	0	0
T178	0	10	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	437522	0	0
T5	23389	1315	0	0
T6	4339	0	0	0
T7	4981	0	0	0
T8	15524	0	0	0
T9	3286	0	0	0
T10	2283	0	0	0
T11	2872	0	0	0
T12	22546	1283	0	0
T13	3317	0	0	0
T14	0	111	0	0
T16	0	2157	0	0
T17	0	183	0	0
T26	2168	0	0	0
T27	0	4182	0	0
T30	0	359	0	0
T33	0	466	0	0
T38	0	308	0	0
T77	0	4150	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	24392267	0	0
T1	689	540	0	0
T2	2316	2195	0	0
T3	1345	1187	0	0
T4	1603	1206	0	0
T5	23389	23330	0	0
T6	4339	4268	0	0
T7	4981	4891	0	0
T8	15524	15471	0	0
T9	3286	2979	0	0
T10	2283	2232	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	172162	0	0
T12	22546	18055	0	0
T14	1903	934	0	0
T15	19643	0	0	0
T27	57398	2948	0	0
T30	0	1190	0	0
T33	0	1509	0	0
T34	0	34	0	0
T38	0	439	0	0
T39	2451	0	0	0
T40	15089	0	0	0
T41	15623	0	0	0
T45	2884	0	0	0
T54	4001	0	0	0
T55	1588	0	0	0
T96	0	623	0	0
T97	0	962	0	0
T176	0	34	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	4442	0	0
T1	689	1	0	0
T2	2316	1	0	0
T3	1345	1	0	0
T4	1603	0	0	0
T5	23389	0	0	0
T6	4339	0	0	0
T7	4981	0	0	0
T8	15524	1	0	0
T9	3286	0	0	0
T10	2283	6	0	0
T13	0	5	0	0
T14	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	160	0	0
T21	43465	40	0	0
T22	0	40	0	0
T23	0	40	0	0
T24	421304	0	0	0
T28	0	20	0	0
T29	0	20	0	0
T30	3251	0	0	0
T31	3544	0	0	0
T32	1869	0	0	0
T33	3983	0	0	0
T34	1796	0	0	0
T35	15666	0	0	0
T36	5200	0	0	0
T37	64360	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	4442	0	0
T1	689	1	0	0
T2	2316	1	0	0
T3	1345	1	0	0
T4	1603	0	0	0
T5	23389	0	0	0
T6	4339	0	0	0
T7	4981	0	0	0
T8	15524	1	0	0
T9	3286	0	0	0
T10	2283	6	0	0
T13	0	5	0	0
T14	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25088886	1011936	0	0
T5	23389	1640	0	0
T6	4339	0	0	0
T7	4981	0	0	0
T8	15524	0	0	0
T9	3286	0	0	0
T10	2283	68	0	0
T11	2872	0	0	0
T12	22546	1194	0	0
T13	3317	165	0	0
T14	0	77	0	0
T15	0	343	0	0
T16	0	3831	0	0
T17	0	402	0	0
T26	2168	5	0	0
T27	0	5541	0	0