Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7810 |
1 |
|
|
T4 |
11 |
|
T55 |
4 |
|
T12 |
100 |
auto[1] |
21239 |
1 |
|
|
T2 |
1 |
|
T3 |
11 |
|
T4 |
9 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12958 |
1 |
|
|
T2 |
1 |
|
T3 |
5 |
|
T4 |
4 |
auto[1] |
16091 |
1 |
|
|
T3 |
6 |
|
T4 |
16 |
|
T5 |
12 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13587 |
1 |
|
|
T3 |
6 |
|
T4 |
9 |
|
T5 |
9 |
auto[1] |
15462 |
1 |
|
|
T2 |
1 |
|
T3 |
5 |
|
T4 |
11 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1715 |
1 |
|
|
T4 |
1 |
|
T55 |
1 |
|
T12 |
21 |
auto[0] |
auto[0] |
auto[1] |
1829 |
1 |
|
|
T55 |
1 |
|
T12 |
25 |
|
T82 |
1 |
auto[0] |
auto[1] |
auto[0] |
4873 |
1 |
|
|
T3 |
5 |
|
T4 |
1 |
|
T5 |
3 |
auto[0] |
auto[1] |
auto[1] |
4541 |
1 |
|
|
T2 |
1 |
|
T4 |
2 |
|
T5 |
2 |
auto[1] |
auto[0] |
auto[0] |
1829 |
1 |
|
|
T4 |
6 |
|
T12 |
22 |
|
T83 |
1 |
auto[1] |
auto[0] |
auto[1] |
2437 |
1 |
|
|
T4 |
4 |
|
T55 |
2 |
|
T12 |
32 |
auto[1] |
auto[1] |
auto[0] |
5170 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
6 |
auto[1] |
auto[1] |
auto[1] |
6655 |
1 |
|
|
T3 |
5 |
|
T4 |
5 |
|
T5 |
6 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7810 |
1 |
|
|
T4 |
11 |
|
T55 |
4 |
|
T12 |
100 |
auto[1] |
21239 |
1 |
|
|
T2 |
1 |
|
T3 |
11 |
|
T4 |
9 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13086 |
1 |
|
|
T2 |
1 |
|
T3 |
5 |
|
T4 |
5 |
auto[1] |
15963 |
1 |
|
|
T3 |
6 |
|
T4 |
15 |
|
T5 |
8 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13706 |
1 |
|
|
T3 |
6 |
|
T4 |
10 |
|
T5 |
6 |
auto[1] |
15343 |
1 |
|
|
T2 |
1 |
|
T3 |
5 |
|
T4 |
10 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1755 |
1 |
|
|
T4 |
2 |
|
T12 |
22 |
|
T82 |
1 |
auto[0] |
auto[0] |
auto[1] |
1879 |
1 |
|
|
T4 |
1 |
|
T55 |
2 |
|
T12 |
27 |
auto[0] |
auto[1] |
auto[0] |
4964 |
1 |
|
|
T3 |
3 |
|
T4 |
1 |
|
T5 |
5 |
auto[0] |
auto[1] |
auto[1] |
4488 |
1 |
|
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
1 |
auto[1] |
auto[0] |
auto[0] |
1767 |
1 |
|
|
T4 |
4 |
|
T55 |
1 |
|
T12 |
27 |
auto[1] |
auto[0] |
auto[1] |
2409 |
1 |
|
|
T4 |
4 |
|
T55 |
1 |
|
T12 |
24 |
auto[1] |
auto[1] |
auto[0] |
5220 |
1 |
|
|
T3 |
3 |
|
T4 |
3 |
|
T5 |
1 |
auto[1] |
auto[1] |
auto[1] |
6567 |
1 |
|
|
T3 |
3 |
|
T4 |
4 |
|
T5 |
7 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7810 |
1 |
|
|
T4 |
11 |
|
T55 |
4 |
|
T12 |
100 |
auto[1] |
21239 |
1 |
|
|
T2 |
1 |
|
T3 |
11 |
|
T4 |
9 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13054 |
1 |
|
|
T2 |
1 |
|
T3 |
7 |
|
T4 |
9 |
auto[1] |
15995 |
1 |
|
|
T3 |
4 |
|
T4 |
11 |
|
T5 |
8 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13845 |
1 |
|
|
T2 |
1 |
|
T3 |
6 |
|
T4 |
12 |
auto[1] |
15204 |
1 |
|
|
T3 |
5 |
|
T4 |
8 |
|
T5 |
5 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1732 |
1 |
|
|
T4 |
3 |
|
T12 |
21 |
|
T82 |
2 |
auto[0] |
auto[0] |
auto[1] |
1786 |
1 |
|
|
T4 |
1 |
|
T55 |
1 |
|
T12 |
22 |
auto[0] |
auto[1] |
auto[0] |
5002 |
1 |
|
|
T2 |
1 |
|
T3 |
5 |
|
T4 |
4 |
auto[0] |
auto[1] |
auto[1] |
4534 |
1 |
|
|
T3 |
2 |
|
T4 |
1 |
|
T5 |
4 |
auto[1] |
auto[0] |
auto[0] |
1907 |
1 |
|
|
T4 |
3 |
|
T55 |
1 |
|
T12 |
26 |
auto[1] |
auto[0] |
auto[1] |
2385 |
1 |
|
|
T4 |
4 |
|
T55 |
2 |
|
T12 |
31 |
auto[1] |
auto[1] |
auto[0] |
5204 |
1 |
|
|
T3 |
1 |
|
T4 |
2 |
|
T5 |
7 |
auto[1] |
auto[1] |
auto[1] |
6499 |
1 |
|
|
T3 |
3 |
|
T4 |
2 |
|
T5 |
1 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7810 |
1 |
|
|
T4 |
11 |
|
T55 |
4 |
|
T12 |
100 |
auto[1] |
21239 |
1 |
|
|
T2 |
1 |
|
T3 |
11 |
|
T4 |
9 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13072 |
1 |
|
|
T2 |
1 |
|
T3 |
9 |
|
T4 |
7 |
auto[1] |
15977 |
1 |
|
|
T3 |
2 |
|
T4 |
13 |
|
T5 |
9 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13675 |
1 |
|
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
8 |
auto[1] |
15374 |
1 |
|
|
T3 |
9 |
|
T4 |
12 |
|
T5 |
9 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1818 |
1 |
|
|
T4 |
1 |
|
T12 |
29 |
|
T82 |
1 |
auto[0] |
auto[0] |
auto[1] |
1753 |
1 |
|
|
T4 |
2 |
|
T55 |
1 |
|
T12 |
23 |
auto[0] |
auto[1] |
auto[0] |
4815 |
1 |
|
|
T2 |
1 |
|
T3 |
2 |
|
T4 |
2 |
auto[0] |
auto[1] |
auto[1] |
4686 |
1 |
|
|
T3 |
7 |
|
T4 |
2 |
|
T5 |
3 |
auto[1] |
auto[0] |
auto[0] |
1797 |
1 |
|
|
T4 |
3 |
|
T55 |
2 |
|
T12 |
24 |
auto[1] |
auto[0] |
auto[1] |
2442 |
1 |
|
|
T4 |
5 |
|
T55 |
1 |
|
T12 |
24 |
auto[1] |
auto[1] |
auto[0] |
5245 |
1 |
|
|
T4 |
2 |
|
T5 |
3 |
|
T7 |
4 |
auto[1] |
auto[1] |
auto[1] |
6493 |
1 |
|
|
T3 |
2 |
|
T4 |
3 |
|
T5 |
6 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7810 |
1 |
|
|
T4 |
11 |
|
T55 |
4 |
|
T12 |
100 |
auto[1] |
21239 |
1 |
|
|
T2 |
1 |
|
T3 |
11 |
|
T4 |
9 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13064 |
1 |
|
|
T2 |
1 |
|
T3 |
5 |
|
T4 |
5 |
auto[1] |
15985 |
1 |
|
|
T3 |
6 |
|
T4 |
15 |
|
T5 |
10 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13753 |
1 |
|
|
T3 |
4 |
|
T4 |
14 |
|
T5 |
15 |
auto[1] |
15296 |
1 |
|
|
T2 |
1 |
|
T3 |
7 |
|
T4 |
6 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1762 |
1 |
|
|
T4 |
3 |
|
T55 |
1 |
|
T12 |
17 |
auto[0] |
auto[0] |
auto[1] |
1783 |
1 |
|
|
T55 |
1 |
|
T12 |
26 |
|
T82 |
1 |
auto[0] |
auto[1] |
auto[0] |
4963 |
1 |
|
|
T3 |
1 |
|
T4 |
2 |
|
T5 |
6 |
auto[0] |
auto[1] |
auto[1] |
4556 |
1 |
|
|
T2 |
1 |
|
T3 |
4 |
|
T5 |
1 |
auto[1] |
auto[0] |
auto[0] |
1750 |
1 |
|
|
T4 |
5 |
|
T55 |
2 |
|
T12 |
17 |
auto[1] |
auto[0] |
auto[1] |
2515 |
1 |
|
|
T4 |
3 |
|
T12 |
40 |
|
T82 |
1 |
auto[1] |
auto[1] |
auto[0] |
5278 |
1 |
|
|
T3 |
3 |
|
T4 |
4 |
|
T5 |
9 |
auto[1] |
auto[1] |
auto[1] |
6442 |
1 |
|
|
T3 |
3 |
|
T4 |
3 |
|
T5 |
1 |
Summary for Variable capture_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for capture_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7810 |
1 |
|
|
T4 |
11 |
|
T55 |
4 |
|
T12 |
100 |
auto[1] |
21239 |
1 |
|
|
T2 |
1 |
|
T3 |
11 |
|
T4 |
9 |
Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13282 |
1 |
|
|
T2 |
1 |
|
T3 |
7 |
|
T4 |
13 |
auto[1] |
15767 |
1 |
|
|
T3 |
4 |
|
T4 |
7 |
|
T5 |
13 |
Summary for Variable wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for wakeup_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13826 |
1 |
|
|
T3 |
3 |
|
T4 |
12 |
|
T5 |
10 |
auto[1] |
15223 |
1 |
|
|
T2 |
1 |
|
T3 |
8 |
|
T4 |
8 |
Summary for Cross wakeup_cross
Samples crossed: enable_cp capture_cp wakeup_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for wakeup_cross
Bins
enable_cp | capture_cp | wakeup_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1746 |
1 |
|
|
T4 |
5 |
|
T55 |
1 |
|
T12 |
31 |
auto[0] |
auto[0] |
auto[1] |
1893 |
1 |
|
|
T4 |
2 |
|
T12 |
24 |
|
T83 |
2 |
auto[0] |
auto[1] |
auto[0] |
4994 |
1 |
|
|
T3 |
2 |
|
T4 |
2 |
|
T5 |
2 |
auto[0] |
auto[1] |
auto[1] |
4649 |
1 |
|
|
T2 |
1 |
|
T3 |
5 |
|
T4 |
4 |
auto[1] |
auto[0] |
auto[0] |
1794 |
1 |
|
|
T4 |
2 |
|
T55 |
2 |
|
T12 |
16 |
auto[1] |
auto[0] |
auto[1] |
2377 |
1 |
|
|
T4 |
2 |
|
T55 |
1 |
|
T12 |
29 |
auto[1] |
auto[1] |
auto[0] |
5292 |
1 |
|
|
T3 |
1 |
|
T4 |
3 |
|
T5 |
8 |
auto[1] |
auto[1] |
auto[1] |
6304 |
1 |
|
|
T3 |
3 |
|
T5 |
5 |
|
T7 |
3 |