Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	536721	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

204090

1

T1

11

T2

7

T3

49

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	387570	1			T1	44		T2	6		T3	101
values[0x0]	176542	1			T1	8		T2	10		T3	57
values[0x1]	176699	1			T1	14		T2	6		T3	44

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	425387	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

315424

1

T1

24

T2

8

T3

74

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3191	1			T4	1		T5	1		T7	2
valid_sources[0x01]	2531	1			T4	1		T26	2		T55	1
valid_sources[0x02]	3058	1			T1	1		T5	2		T55	1
valid_sources[0x03]	2872	1			T2	2		T5	2		T7	2
valid_sources[0x04]	2384	1			T1	2		T4	6		T5	1
valid_sources[0x05]	2874	1			T3	1		T5	1		T7	3
valid_sources[0x06]	2617	1			T3	1		T5	3		T55	3
valid_sources[0x07]	2748	1			T3	1		T5	2		T7	3
valid_sources[0x08]	2390	1			T3	1		T26	4		T55	1
valid_sources[0x09]	2680	1			T7	1		T26	3		T55	1
valid_sources[0x0a]	2561	1			T3	1		T4	2		T5	1
valid_sources[0x0b]	2427	1			T1	1		T3	2		T5	3
valid_sources[0x0c]	2391	1			T4	1		T7	2		T26	2
valid_sources[0x0d]	3173	1			T1	1		T5	3		T7	2
valid_sources[0x0e]	2555	1			T5	1		T7	1		T26	2
valid_sources[0x0f]	4257	1			T3	1		T7	2		T8	4
valid_sources[0x10]	2687	1			T5	1		T7	1		T26	1
valid_sources[0x11]	5700	1			T4	2		T5	1		T7	3
valid_sources[0x12]	2570	1			T5	2		T12	14		T14	58
valid_sources[0x13]	2639	1			T1	1		T4	2		T5	1
valid_sources[0x14]	2648	1			T5	1		T7	1		T26	1
valid_sources[0x15]	3013	1			T1	1		T4	1		T5	1
valid_sources[0x16]	2423	1			T3	1		T5	1		T55	1
valid_sources[0x17]	2600	1			T5	2		T7	1		T12	27
valid_sources[0x18]	2911	1			T7	1		T12	24		T14	49
valid_sources[0x19]	2607	1			T3	2		T4	1		T5	1
valid_sources[0x1a]	2711	1			T3	1		T4	7		T5	1
valid_sources[0x1b]	2598	1			T3	2		T5	2		T7	1
valid_sources[0x1c]	2506	1			T5	5		T7	2		T26	1
valid_sources[0x1d]	3282	1			T4	2		T5	2		T7	1
valid_sources[0x1e]	2309	1			T2	4		T3	3		T5	2
valid_sources[0x1f]	2313	1			T5	3		T7	1		T26	1
valid_sources[0x20]	2979	1			T1	4		T5	1		T7	2
valid_sources[0x21]	2712	1			T1	4		T3	1		T5	1
valid_sources[0x22]	2970	1			T3	1		T5	2		T7	1
valid_sources[0x23]	3252	1			T3	2		T5	1		T12	34
valid_sources[0x24]	3220	1			T1	1		T3	1		T5	2
valid_sources[0x25]	2448	1			T26	2		T12	20		T83	3
valid_sources[0x26]	2657	1			T3	3		T4	2		T5	1
valid_sources[0x27]	3122	1			T5	2		T26	1		T43	1
valid_sources[0x28]	2384	1			T4	4		T7	1		T26	1
valid_sources[0x29]	2658	1			T4	3		T12	22		T14	58
valid_sources[0x2a]	3005	1			T3	1		T4	2		T7	1
valid_sources[0x2b]	2461	1			T3	2		T5	1		T7	1
valid_sources[0x2c]	3363	1			T7	1		T12	30		T83	2
valid_sources[0x2d]	2345	1			T4	2		T26	2		T55	1
valid_sources[0x2e]	2456	1			T4	2		T5	1		T7	1
valid_sources[0x2f]	4459	1			T5	1		T7	2		T55	1
valid_sources[0x30]	2597	1			T3	1		T5	3		T7	1
valid_sources[0x31]	3222	1			T7	1		T26	3		T12	23
valid_sources[0x32]	2647	1			T3	1		T26	2		T12	18
valid_sources[0x33]	3403	1			T1	2		T5	3		T7	2
valid_sources[0x34]	2571	1			T5	1		T7	3		T12	23
valid_sources[0x35]	2793	1			T5	3		T7	2		T26	1
valid_sources[0x36]	2625	1			T3	2		T5	1		T7	1
valid_sources[0x37]	2511	1			T4	4		T5	3		T7	1
valid_sources[0x38]	2610	1			T3	1		T5	2		T26	2
valid_sources[0x39]	5077	1			T3	1		T4	2		T7	2
valid_sources[0x3a]	3164	1			T2	1		T4	1		T5	1
valid_sources[0x3b]	2445	1			T2	4		T3	2		T7	1
valid_sources[0x3c]	3532	1			T5	3		T7	1		T26	2
valid_sources[0x3d]	2472	1			T5	2		T7	7		T26	4
valid_sources[0x3e]	2859	1			T5	2		T7	2		T55	1
valid_sources[0x3f]	2621	1			T3	1		T5	2		T7	1
valid_sources[0x40]	3357	1			T3	1		T4	3		T5	1
valid_sources[0x41]	2386	1			T3	1		T4	1		T5	1
valid_sources[0x42]	3814	1			T1	2		T3	3		T5	1
valid_sources[0x43]	2384	1			T3	2		T4	1		T5	4
valid_sources[0x44]	2328	1			T4	4		T5	3		T26	4
valid_sources[0x45]	3623	1			T1	1		T7	2		T26	1
valid_sources[0x46]	2913	1			T7	1		T12	21		T82	6
valid_sources[0x47]	4763	1			T3	2		T5	1		T7	1
valid_sources[0x48]	4119	1			T3	1		T5	1		T26	2
valid_sources[0x49]	3490	1			T5	1		T7	1		T26	4
valid_sources[0x4a]	2610	1			T4	2		T5	1		T26	1
valid_sources[0x4b]	3467	1			T1	1		T3	2		T4	1
valid_sources[0x4c]	2734	1			T1	1		T3	2		T4	1
valid_sources[0x4d]	2607	1			T3	1		T4	3		T5	2
valid_sources[0x4e]	3217	1			T3	2		T4	3		T7	1
valid_sources[0x4f]	2648	1			T4	5		T5	2		T7	1
valid_sources[0x50]	2430	1			T3	2		T5	2		T55	1
valid_sources[0x51]	2944	1			T4	2		T7	2		T26	1
valid_sources[0x52]	3491	1			T4	3		T5	1		T26	3
valid_sources[0x53]	2478	1			T4	4		T5	1		T7	2
valid_sources[0x54]	2460	1			T1	2		T3	3		T4	1
valid_sources[0x55]	2439	1			T4	2		T5	1		T7	2
valid_sources[0x56]	2274	1			T5	2		T7	3		T26	2
valid_sources[0x57]	2719	1			T5	1		T7	4		T26	1
valid_sources[0x58]	2653	1			T3	1		T4	1		T5	2
valid_sources[0x59]	3346	1			T5	4		T7	1		T55	3
valid_sources[0x5a]	2361	1			T1	1		T7	2		T26	2
valid_sources[0x5b]	4483	1			T5	1		T12	15		T14	61
valid_sources[0x5c]	2370	1			T3	2		T5	1		T26	2
valid_sources[0x5d]	2421	1			T5	2		T7	2		T12	25
valid_sources[0x5e]	2436	1			T3	6		T5	4		T7	2
valid_sources[0x5f]	2578	1			T1	1		T4	5		T5	1
valid_sources[0x60]	3179	1			T3	1		T5	2		T12	19
valid_sources[0x61]	2595	1			T5	2		T7	2		T26	1
valid_sources[0x62]	2979	1			T4	2		T5	1		T55	1
valid_sources[0x63]	3185	1			T3	1		T5	2		T7	2
valid_sources[0x64]	4462	1			T3	1		T5	1		T26	1
valid_sources[0x65]	2619	1			T1	1		T5	2		T12	21
valid_sources[0x66]	2527	1			T5	2		T7	2		T26	2
valid_sources[0x67]	2631	1			T3	2		T5	2		T7	1
valid_sources[0x68]	4685	1			T3	1		T4	1		T5	2
valid_sources[0x69]	2567	1			T1	2		T5	1		T7	3
valid_sources[0x6a]	2724	1			T4	2		T5	2		T12	25
valid_sources[0x6b]	3634	1			T4	4		T5	2		T55	1
valid_sources[0x6c]	2453	1			T5	1		T26	1		T55	1
valid_sources[0x6d]	2639	1			T1	2		T5	1		T7	1
valid_sources[0x6e]	4908	1			T3	1		T4	1		T5	2
valid_sources[0x6f]	2465	1			T5	1		T7	3		T26	4
valid_sources[0x70]	2795	1			T1	1		T5	1		T7	2
valid_sources[0x71]	2471	1			T7	1		T12	26		T82	2
valid_sources[0x72]	2714	1			T3	2		T4	3		T5	1
valid_sources[0x73]	2439	1			T3	1		T5	2		T26	1
valid_sources[0x74]	3494	1			T2	2		T4	3		T5	1
valid_sources[0x75]	2763	1			T4	2		T7	3		T26	1
valid_sources[0x76]	3482	1			T5	1		T7	1		T26	2
valid_sources[0x77]	2501	1			T3	1		T4	1		T7	1
valid_sources[0x78]	2393	1			T3	1		T5	2		T12	25
valid_sources[0x79]	3185	1			T3	2		T5	4		T7	1
valid_sources[0x7a]	2413	1			T3	2		T5	2		T7	1
valid_sources[0x7b]	2741	1			T5	1		T55	1		T12	16
valid_sources[0x7c]	2789	1			T1	2		T3	2		T4	1
valid_sources[0x7d]	2483	1			T3	2		T4	1		T5	1
valid_sources[0x7e]	3311	1			T3	1		T4	1		T5	2
valid_sources[0x7f]	3003	1			T3	2		T4	2		T5	3
valid_sources[0x80]	2455	1			T3	1		T4	1		T5	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

103383

1

T1

9

T2

2

T3

18

values[0x0]

all_enables

biggest_size

65099

1

T1

2

T2

1

T3

24

values[0x1]

all_enables

biggest_size

35608

1

T2

4

T3

7

T4

10