SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34942 | 1 | T23 | 1 | T24 | 289 | T184 | 358 | ||||
others[1] | 34734 | 1 | T24 | 280 | T184 | 410 | T164 | 386 | ||||
others[2] | 34941 | 1 | T24 | 335 | T184 | 372 | T164 | 377 | ||||
others[3] | 58737 | 1 | T23 | 1 | T24 | 499 | T184 | 721 | ||||
false | 20169 | 1 | T1 | 3 | T3 | 22 | T5 | 34 | ||||
true | 30479 | 1 | T1 | 5 | T2 | 5 | T3 | 23 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34978 | 1 | T24 | 296 | T184 | 398 | T164 | 416 | ||||
others[1] | 34864 | 1 | T23 | 1 | T24 | 294 | T184 | 376 | ||||
others[2] | 35205 | 1 | T1 | 1 | T24 | 296 | T184 | 375 | ||||
others[3] | 58386 | 1 | T24 | 520 | T184 | 725 | T164 | 690 | ||||
false | 12667 | 1 | T1 | 3 | T3 | 11 | T5 | 17 | ||||
true | 23031 | 1 | T1 | 6 | T2 | 5 | T3 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 656 | 1 | T26 | 9 | T12 | 9 | T88 | 5 | ||||
others[1] | 736 | 1 | T26 | 5 | T12 | 4 | T88 | 7 | ||||
others[2] | 715 | 1 | T26 | 4 | T12 | 4 | T88 | 6 | ||||
others[3] | 1175 | 1 | T1 | 1 | T26 | 3 | T12 | 7 | ||||
false | 14163 | 1 | T1 | 7 | T2 | 5 | T3 | 1 | ||||
true | 4211 | 1 | T1 | 4 | T26 | 2 | T12 | 56 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |