Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	27120617	16834	0	0
intr_enable_rd_A	27120617	48244	0	0
reset_en_rd_A	27120617	1923	0	0
reset_en_regwen_rd_A	27120617	1678	0	0
wake_info_capture_dis_rd_A	27120617	1765	0	0
wakeup_en_rd_A	27120617	2732	0	0
wakeup_en_regwen_rd_A	27120617	1698	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27120617	16834	0	0
T12	162706	6	0	0
T13	2311	0	0	0
T14	704360	26	0	0
T22	0	32	0	0
T25	1159	0	0	0
T40	875	0	0	0
T44	1756	0	0	0
T51	0	14	0	0
T52	0	69	0	0
T53	0	4	0	0
T66	0	33	0	0
T81	1740	0	0	0
T82	6666	0	0	0
T83	9170	0	0	0
T88	3596	0	0	0
T89	0	9	0	0
T148	0	10	0	0
T149	0	21	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27120617	48244	0	0
T7	9890	34	0	0
T8	6296	4	0	0
T9	14881	0	0	0
T10	1338	0	0	0
T11	2229	0	0	0
T12	162706	864	0	0
T14	0	3371	0	0
T24	0	153	0	0
T26	2352	0	0	0
T38	0	19	0	0
T43	1461	0	0	0
T55	8967	0	0	0
T81	0	6	0	0
T82	6666	0	0	0
T87	0	44	0	0
T140	0	6	0	0
T143	0	32	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27120617	1923	0	0
T12	162706	14	0	0
T13	2311	0	0	0
T14	704360	24	0	0
T25	1159	0	0	0
T40	875	0	0	0
T44	1756	0	0	0
T79	0	14	0	0
T81	1740	0	0	0
T82	6666	0	0	0
T83	9170	0	0	0
T88	3596	0	0	0
T89	0	1	0	0
T150	0	9	0	0
T151	0	6	0	0
T152	0	18	0	0
T153	0	9	0	0
T154	0	10	0	0
T155	0	12	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27120617	1678	0	0
T12	162706	1	0	0
T13	2311	0	0	0
T14	704360	12	0	0
T25	1159	0	0	0
T40	875	0	0	0
T44	1756	0	0	0
T67	0	7	0	0
T79	0	8	0	0
T81	1740	0	0	0
T82	6666	0	0	0
T83	9170	0	0	0
T88	3596	0	0	0
T89	0	4	0	0
T90	0	1	0	0
T152	0	9	0	0
T153	0	9	0	0
T155	0	12	0	0
T156	0	12	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27120617	1765	0	0
T12	162706	22	0	0
T13	2311	0	0	0
T14	704360	17	0	0
T25	1159	0	0	0
T40	875	0	0	0
T44	1756	0	0	0
T67	0	9	0	0
T79	0	22	0	0
T81	1740	0	0	0
T82	6666	0	0	0
T83	9170	0	0	0
T88	3596	0	0	0
T89	0	8	0	0
T151	0	6	0	0
T152	0	14	0	0
T154	0	3	0	0
T155	0	10	0	0
T156	0	7	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27120617	2732	0	0
T12	162706	9	0	0
T13	2311	0	0	0
T14	704360	17	0	0
T25	1159	0	0	0
T40	875	0	0	0
T44	1756	0	0	0
T67	0	5	0	0
T79	0	5	0	0
T81	1740	0	0	0
T82	6666	0	0	0
T83	9170	0	0	0
T88	3596	0	0	0
T89	0	6	0	0
T152	0	13	0	0
T153	0	9	0	0
T154	0	6	0	0
T155	0	18	0	0
T156	0	2	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27120617	1698	0	0
T12	162706	4	0	0
T13	2311	0	0	0
T14	704360	14	0	0
T25	1159	0	0	0
T40	875	0	0	0
T44	1756	0	0	0
T79	0	10	0	0
T81	1740	0	0	0
T82	6666	0	0	0
T83	9170	0	0	0
T88	3596	0	0	0
T89	0	8	0	0
T151	0	5	0	0
T152	0	10	0	0
T153	0	9	0	0
T154	0	6	0	0
T155	0	22	0	0
T156	0	13	0	0