Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	79604712	152083	0	0
StatusRise_A	79604712	169780	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79604712	152083	0	0
T1	9285	21	0	0
T2	4257	12	0	0
T3	37281	42	0	0
T4	24282	50	0	0
T5	51273	70	0	0
T6	4659	0	0	0
T7	29670	72	0	0
T8	18888	18	0	0
T9	44643	3	0	0
T10	4014	3	0	0
T26	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79604712	169780	0	0
T1	9285	27	0	0
T2	4257	15	0	0
T3	37281	45	0	0
T4	24282	52	0	0
T5	51273	76	0	0
T6	4659	12	0	0
T7	29670	78	0	0
T8	18888	21	0	0
T9	44643	6	0	0
T10	4014	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	26534904	56458	0	0
StatusRise_A	26534904	62854	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26534904	56458	0	0
T1	3095	7	0	0
T2	1419	4	0	0
T3	12427	17	0	0
T4	8094	20	0	0
T5	17091	28	0	0
T6	1553	0	0	0
T7	9890	30	0	0
T8	6296	7	0	0
T9	14881	1	0	0
T10	1338	1	0	0
T26	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26534904	62854	0	0
T1	3095	9	0	0
T2	1419	5	0	0
T3	12427	18	0	0
T4	8094	21	0	0
T5	17091	30	0	0
T6	1553	4	0	0
T7	9890	32	0	0
T8	6296	8	0	0
T9	14881	2	0	0
T10	1338	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	26534904	56458	0	0
StatusRise_A	26534904	62854	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26534904	56458	0	0
T1	3095	7	0	0
T2	1419	4	0	0
T3	12427	17	0	0
T4	8094	20	0	0
T5	17091	28	0	0
T6	1553	0	0	0
T7	9890	30	0	0
T8	6296	7	0	0
T9	14881	1	0	0
T10	1338	1	0	0
T26	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26534904	62854	0	0
T1	3095	9	0	0
T2	1419	5	0	0
T3	12427	18	0	0
T4	8094	21	0	0
T5	17091	30	0	0
T6	1553	4	0	0
T7	9890	32	0	0
T8	6296	8	0	0
T9	14881	2	0	0
T10	1338	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	26534904	39167	0	0
StatusRise_A	26534904	44072	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26534904	39167	0	0
T1	3095	7	0	0
T2	1419	4	0	0
T3	12427	8	0	0
T4	8094	10	0	0
T5	17091	14	0	0
T6	1553	0	0	0
T7	9890	12	0	0
T8	6296	4	0	0
T9	14881	1	0	0
T10	1338	1	0	0
T26	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26534904	44072	0	0
T1	3095	9	0	0
T2	1419	5	0	0
T3	12427	9	0	0
T4	8094	10	0	0
T5	17091	16	0	0
T6	1553	4	0	0
T7	9890	14	0	0
T8	6296	5	0	0
T9	14881	2	0	0
T10	1338	3	0	0