Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	26535488	5298	0	0
EscTimeoutStoppedByClReset_A	26534904	3746540	0	0
EscTimeoutTriggersReset_A	5338943	323	0	0
RomAllowActiveState_A	26534904	62460	0	0
RomAllowCheckGoodState_A	26534904	62511	0	0
RomBlockActiveState_A	26534904	31874	0	0
RomBlockCheckGoodState_A	26534904	438141	0	0
RomIntgChkDisFalse_A	26534904	25916352	0	0
RomIntgChkDisTrue_A	26534904	73222	0	0
RstreqChkEsctimeout_A	26534904	4402	0	0
RstreqChkFsmterm_A	26534904	140	0	0
RstreqChkGlbesc_A	26534904	4402	0	0
RstreqChkMainpd_A	26534904	1070391	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26535488	5298	0	0
T9	14882	31	0	0
T10	1338	0	0	0
T11	2229	0	0	0
T12	162707	0	0	0
T13	2312	0	0	0
T26	2352	0	0	0
T40	875	0	0	0
T43	1462	0	0	0
T55	8968	0	0	0
T82	6667	0	0	0
T92	0	45	0	0
T93	0	5	0	0
T107	0	47	0	0
T157	0	4	0	0
T158	0	53	0	0
T159	0	13	0	0
T160	0	9	0	0
T161	0	156	0	0
T162	0	122	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26534904	3746540	0	0
T1	3095	176	0	0
T2	1419	74	0	0
T3	12427	1882	0	0
T4	8094	2085	0	0
T5	17091	3460	0	0
T6	1553	22	0	0
T7	9890	1536	0	0
T8	6296	454	0	0
T9	14881	24	0	0
T10	1338	18	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5338943	323	0	0
T9	647	2	0	0
T10	220	4	0	0
T11	190	3	0	0
T12	54790	0	0	0
T13	211	0	0	0
T26	603	0	0	0
T40	307	0	0	0
T43	505	0	0	0
T55	987	0	0	0
T82	1078	0	0	0
T92	0	3	0	0
T93	0	3	0	0
T95	0	3	0	0
T107	0	2	0	0
T110	0	2	0	0
T157	0	4	0	0
T163	0	2	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26534904	62460	0	0
T1	3095	9	0	0
T2	1419	5	0	0
T3	12427	18	0	0
T4	8094	21	0	0
T5	17091	30	0	0
T6	1553	4	0	0
T7	9890	32	0	0
T8	6296	8	0	0
T9	14881	2	0	0
T10	1338	3	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26534904	62511	0	0
T1	3095	9	0	0
T2	1419	5	0	0
T3	12427	18	0	0
T4	8094	21	0	0
T5	17091	30	0	0
T6	1553	4	0	0
T7	9890	32	0	0
T8	6296	8	0	0
T9	14881	2	0	0
T10	1338	3	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26534904	31874	0	0
T1	3095	709	0	0
T2	1419	0	0	0
T3	12427	0	0	0
T4	8094	0	0	0
T5	17091	0	0	0
T6	1553	0	0	0
T7	9890	0	0	0
T8	6296	0	0	0
T9	14881	0	0	0
T10	1338	0	0	0
T23	0	1447	0	0
T47	0	1138	0	0
T101	0	637	0	0
T164	0	16	0	0
T165	0	14	0	0
T166	0	3	0	0
T167	0	1168	0	0
T168	0	3	0	0
T169	0	932	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26534904	438141	0	0
T1	3095	358	0	0
T2	1419	0	0	0
T3	12427	253	0	0
T4	8094	0	0	0
T5	17091	390	0	0
T6	1553	0	0	0
T7	9890	390	0	0
T8	6296	115	0	0
T9	14881	0	0	0
T10	1338	0	0	0
T12	0	1306	0	0
T14	0	3988	0	0
T22	0	1423	0	0
T23	0	878	0	0
T38	0	92	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26534904	25916352	0	0
T1	3095	2651	0	0
T2	1419	1110	0	0
T3	12427	12375	0	0
T4	8094	8002	0	0
T5	17091	16939	0	0
T6	1553	1244	0	0
T7	9890	9748	0	0
T8	6296	6230	0	0
T9	14881	14794	0	0
T10	1338	1217	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26534904	73222	0	0
T1	3095	270	0	0
T2	1419	0	0	0
T3	12427	0	0	0
T4	8094	0	0	0
T5	17091	0	0	0
T6	1553	0	0	0
T7	9890	0	0	0
T8	6296	0	0	0
T9	14881	0	0	0
T10	1338	0	0	0
T23	0	210	0	0
T24	0	1209	0	0
T47	0	138	0	0
T101	0	105	0	0
T166	0	584	0	0
T167	0	337	0	0
T169	0	251	0	0
T170	0	196	0	0
T171	0	935	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26534904	4402	0	0
T1	3095	3	0	0
T2	1419	0	0	0
T3	12427	0	0	0
T4	8094	0	0	0
T5	17091	0	0	0
T6	1553	0	0	0
T7	9890	0	0	0
T8	6296	0	0	0
T9	14881	1	0	0
T10	1338	1	0	0
T11	0	1	0	0
T12	0	52	0	0
T13	0	2	0	0
T14	0	42	0	0
T25	0	3	0	0
T39	0	5	0	0
T40	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26534904	140	0	0
T19	9303	20	0	0
T20	0	20	0	0
T21	0	40	0	0
T27	0	40	0	0
T28	0	20	0	0
T29	13611	0	0	0
T30	75134	0	0	0
T31	1640	0	0	0
T32	14972	0	0	0
T33	3242	0	0	0
T34	531542	0	0	0
T35	7066	0	0	0
T36	1573	0	0	0
T37	15336	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26534904	4402	0	0
T1	3095	3	0	0
T2	1419	0	0	0
T3	12427	0	0	0
T4	8094	0	0	0
T5	17091	0	0	0
T6	1553	0	0	0
T7	9890	0	0	0
T8	6296	0	0	0
T9	14881	1	0	0
T10	1338	1	0	0
T11	0	1	0	0
T12	0	52	0	0
T13	0	2	0	0
T14	0	42	0	0
T25	0	3	0	0
T39	0	5	0	0
T40	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26534904	1070391	0	0
T1	3095	664	0	0
T2	1419	0	0	0
T3	12427	754	0	0
T4	8094	0	0	0
T5	17091	1535	0	0
T6	1553	10	0	0
T7	9890	652	0	0
T8	6296	206	0	0
T9	14881	0	0	0
T10	1338	0	0	0
T12	0	3302	0	0
T14	0	18389	0	0
T25	0	25	0	0
T38	0	207	0	0