Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	551288	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

212253

1

T1

20

T2

497

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	405226	1			T1	35		T2	1146		T3	1
values[0x0]	179048	1			T1	11		T2	454		T4	63
values[0x1]	179267	1			T1	5		T2	422		T4	57

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	436578	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

326963

1

T1

24

T2

791

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2441	1			T2	10		T9	1		T23	2
valid_sources[0x01]	2816	1			T2	5		T23	6		T20	34
valid_sources[0x02]	2618	1			T2	8		T23	1		T25	2
valid_sources[0x03]	3142	1			T2	6		T23	1		T41	6
valid_sources[0x04]	3467	1			T1	1		T2	9		T23	1
valid_sources[0x05]	2646	1			T2	11		T9	2		T81	1
valid_sources[0x06]	2488	1			T2	10		T10	1		T23	3
valid_sources[0x07]	2380	1			T2	3		T9	1		T23	3
valid_sources[0x08]	2478	1			T1	3		T2	7		T23	1
valid_sources[0x09]	2744	1			T2	5		T23	2		T81	1
valid_sources[0x0a]	4416	1			T2	9		T23	2		T25	2
valid_sources[0x0b]	2386	1			T2	8		T9	18		T23	3
valid_sources[0x0c]	2533	1			T2	8		T9	2		T23	8
valid_sources[0x0d]	2335	1			T2	11		T23	3		T20	19
valid_sources[0x0e]	2471	1			T1	1		T2	12		T10	1
valid_sources[0x0f]	2527	1			T2	9		T23	3		T24	2
valid_sources[0x10]	2876	1			T1	1		T2	6		T4	5
valid_sources[0x11]	2954	1			T2	8		T23	2		T81	3
valid_sources[0x12]	2959	1			T2	10		T10	2		T25	1
valid_sources[0x13]	2914	1			T2	5		T9	1		T10	1
valid_sources[0x14]	2645	1			T2	6		T10	1		T23	1
valid_sources[0x15]	2356	1			T2	7		T10	1		T25	2
valid_sources[0x16]	2487	1			T1	3		T2	6		T36	3
valid_sources[0x17]	2852	1			T1	2		T2	3		T23	4
valid_sources[0x18]	2510	1			T2	11		T9	4		T23	4
valid_sources[0x19]	4835	1			T2	5		T23	5		T14	1
valid_sources[0x1a]	2447	1			T2	12		T25	2		T20	14
valid_sources[0x1b]	2492	1			T2	5		T23	3		T41	13
valid_sources[0x1c]	2488	1			T2	13		T23	5		T81	1
valid_sources[0x1d]	2496	1			T2	8		T23	2		T24	1
valid_sources[0x1e]	2903	1			T2	7		T4	5		T9	1
valid_sources[0x1f]	3176	1			T2	7		T23	1		T81	1
valid_sources[0x20]	2686	1			T2	4		T23	3		T36	2
valid_sources[0x21]	2450	1			T2	8		T9	2		T23	1
valid_sources[0x22]	2470	1			T2	4		T9	3		T23	4
valid_sources[0x23]	2500	1			T2	6		T23	6		T20	14
valid_sources[0x24]	2613	1			T1	2		T2	8		T23	3
valid_sources[0x25]	2527	1			T2	9		T23	1		T41	13
valid_sources[0x26]	2735	1			T2	7		T23	5		T81	1
valid_sources[0x27]	2500	1			T2	5		T23	5		T29	3
valid_sources[0x28]	2599	1			T2	4		T4	5		T23	2
valid_sources[0x29]	2294	1			T2	12		T23	7		T25	1
valid_sources[0x2a]	14293	1			T2	9		T10	1		T23	4
valid_sources[0x2b]	3461	1			T2	7		T23	3		T25	1
valid_sources[0x2c]	3807	1			T2	10		T23	3		T53	164
valid_sources[0x2d]	2898	1			T2	11		T9	2		T23	3
valid_sources[0x2e]	3924	1			T2	8		T23	5		T20	20
valid_sources[0x2f]	2808	1			T2	4		T20	21		T138	5
valid_sources[0x30]	2583	1			T2	4		T23	3		T29	4
valid_sources[0x31]	3233	1			T2	7		T23	2		T25	2
valid_sources[0x32]	4440	1			T2	10		T23	6		T81	2
valid_sources[0x33]	2435	1			T2	10		T9	9		T23	10
valid_sources[0x34]	3533	1			T2	8		T23	3		T25	1
valid_sources[0x35]	2624	1			T2	10		T23	3		T25	2
valid_sources[0x36]	3966	1			T2	8		T23	5		T20	27
valid_sources[0x37]	2499	1			T2	6		T23	3		T20	38
valid_sources[0x38]	2532	1			T2	14		T23	4		T81	1
valid_sources[0x39]	2472	1			T2	8		T23	5		T81	2
valid_sources[0x3a]	2753	1			T2	4		T23	2		T81	2
valid_sources[0x3b]	2563	1			T2	8		T4	5		T9	9
valid_sources[0x3c]	2478	1			T2	8		T9	1		T23	3
valid_sources[0x3d]	2622	1			T2	9		T23	2		T81	4
valid_sources[0x3e]	2330	1			T2	7		T23	2		T25	1
valid_sources[0x3f]	2719	1			T2	10		T23	2		T14	1
valid_sources[0x40]	2539	1			T2	14		T23	3		T25	1
valid_sources[0x41]	2944	1			T2	10		T23	6		T25	1
valid_sources[0x42]	2448	1			T2	6		T9	3		T23	1
valid_sources[0x43]	3640	1			T2	7		T23	5		T25	1
valid_sources[0x44]	2396	1			T2	6		T23	3		T20	19
valid_sources[0x45]	2297	1			T2	5		T9	4		T23	1
valid_sources[0x46]	3627	1			T2	10		T14	1		T81	1
valid_sources[0x47]	2751	1			T2	6		T23	7		T80	43
valid_sources[0x48]	2649	1			T2	7		T23	2		T36	9
valid_sources[0x49]	2543	1			T2	4		T6	35		T23	6
valid_sources[0x4a]	3399	1			T2	14		T23	1		T81	2
valid_sources[0x4b]	2590	1			T2	3		T23	5		T20	15
valid_sources[0x4c]	4986	1			T2	9		T6	24		T23	2
valid_sources[0x4d]	5065	1			T2	8		T9	1		T10	1
valid_sources[0x4e]	3511	1			T2	10		T10	1		T81	1
valid_sources[0x4f]	2724	1			T2	8		T4	5		T23	2
valid_sources[0x50]	4970	1			T1	3		T2	6		T13	2224
valid_sources[0x51]	2595	1			T2	6		T20	15		T138	4
valid_sources[0x52]	3264	1			T2	5		T23	1		T25	1
valid_sources[0x53]	2550	1			T2	8		T23	3		T20	24
valid_sources[0x54]	4253	1			T2	9		T23	4		T25	2
valid_sources[0x55]	3338	1			T2	6		T10	2		T23	5
valid_sources[0x56]	3659	1			T2	5		T23	1		T25	2
valid_sources[0x57]	3290	1			T2	7		T23	2		T25	1
valid_sources[0x58]	2739	1			T2	10		T3	1		T24	1
valid_sources[0x59]	2812	1			T2	9		T23	2		T81	2
valid_sources[0x5a]	2642	1			T2	12		T23	6		T25	3
valid_sources[0x5b]	3273	1			T2	4		T23	2		T14	2
valid_sources[0x5c]	2460	1			T2	4		T23	6		T36	4
valid_sources[0x5d]	2277	1			T2	7		T9	4		T23	3
valid_sources[0x5e]	2489	1			T2	9		T23	2		T81	1
valid_sources[0x5f]	2605	1			T2	7		T23	5		T25	1
valid_sources[0x60]	2875	1			T2	6		T9	7		T23	6
valid_sources[0x61]	2622	1			T2	9		T23	8		T24	2
valid_sources[0x62]	2680	1			T2	4		T23	5		T28	1
valid_sources[0x63]	2561	1			T2	6		T23	3		T37	111
valid_sources[0x64]	3336	1			T2	12		T23	1		T81	2
valid_sources[0x65]	2746	1			T2	12		T10	2		T23	2
valid_sources[0x66]	4162	1			T2	2		T23	6		T25	1
valid_sources[0x67]	3290	1			T2	10		T9	5		T10	1
valid_sources[0x68]	2777	1			T2	9		T23	2		T25	2
valid_sources[0x69]	7292	1			T1	5		T2	10		T23	2
valid_sources[0x6a]	4561	1			T2	7		T23	2		T25	2
valid_sources[0x6b]	4527	1			T2	12		T25	1		T20	21
valid_sources[0x6c]	2762	1			T2	11		T23	3		T25	2
valid_sources[0x6d]	3110	1			T2	11		T23	2		T41	11
valid_sources[0x6e]	4599	1			T2	4		T9	2		T23	3
valid_sources[0x6f]	2461	1			T2	7		T23	1		T36	6
valid_sources[0x70]	2577	1			T2	13		T23	9		T25	1
valid_sources[0x71]	3093	1			T1	2		T2	7		T23	2
valid_sources[0x72]	2709	1			T2	18		T9	1		T23	6
valid_sources[0x73]	2543	1			T2	5		T9	1		T23	3
valid_sources[0x74]	4349	1			T2	11		T9	4		T23	5
valid_sources[0x75]	2676	1			T2	7		T23	6		T20	27
valid_sources[0x76]	2500	1			T2	7		T5	24		T23	3
valid_sources[0x77]	2830	1			T2	13		T4	5		T23	2
valid_sources[0x78]	3221	1			T1	4		T2	7		T9	2
valid_sources[0x79]	3605	1			T2	6		T9	2		T23	5
valid_sources[0x7a]	3509	1			T2	4		T23	1		T24	1
valid_sources[0x7b]	2461	1			T2	10		T9	5		T23	3
valid_sources[0x7c]	3114	1			T2	10		T23	3		T20	34
valid_sources[0x7d]	2558	1			T2	7		T9	1		T23	2
valid_sources[0x7e]	2331	1			T2	10		T23	4		T41	12
valid_sources[0x7f]	3357	1			T2	12		T23	3		T81	2
valid_sources[0x80]	3278	1			T2	6		T23	1		T81	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

110127

1

T1

13

T2

261

T3

1

values[0x0]

all_enables

biggest_size

66381

1

T1

7

T2

163

T4

20

values[0x1]

all_enables

biggest_size

35745

1

T2

73

T4

8

T5

1