SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34674 | 1 | T23 | 299 | T36 | 1 | T137 | 389 | ||||
others[1] | 35003 | 1 | T23 | 306 | T137 | 402 | T138 | 390 | ||||
others[2] | 34584 | 1 | T6 | 1 | T23 | 287 | T24 | 1 | ||||
others[3] | 57839 | 1 | T23 | 502 | T24 | 1 | T137 | 693 | ||||
false | 20759 | 1 | T2 | 76 | T6 | 2 | T9 | 28 | ||||
true | 31105 | 1 | T1 | 5 | T2 | 96 | T3 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34659 | 1 | T23 | 284 | T137 | 397 | T138 | 408 | ||||
others[1] | 35004 | 1 | T23 | 295 | T137 | 395 | T138 | 378 | ||||
others[2] | 34786 | 1 | T6 | 1 | T23 | 307 | T137 | 405 | ||||
others[3] | 57522 | 1 | T23 | 503 | T24 | 2 | T137 | 665 | ||||
false | 12966 | 1 | T2 | 38 | T6 | 4 | T9 | 14 | ||||
true | 23360 | 1 | T1 | 5 | T2 | 58 | T3 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 760 | 1 | T2 | 1 | T13 | 1 | T25 | 1 | ||||
others[1] | 727 | 1 | T2 | 2 | T13 | 2 | T37 | 1 | ||||
others[2] | 765 | 1 | T2 | 2 | T30 | 2 | T20 | 1 | ||||
others[3] | 1252 | 1 | T2 | 5 | T13 | 2 | T25 | 2 | ||||
false | 14811 | 1 | T1 | 5 | T2 | 55 | T3 | 6 | ||||
true | 4587 | 1 | T2 | 25 | T6 | 3 | T13 | 16 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |