Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	27211304	16412	0	0
intr_enable_rd_A	27211304	42562	0	0
reset_en_rd_A	27211304	1453	0	0
reset_en_regwen_rd_A	27211304	1252	0	0
wake_info_capture_dis_rd_A	27211304	1373	0	0
wakeup_en_rd_A	27211304	2080	0	0
wakeup_en_regwen_rd_A	27211304	1399	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27211304	16412	0	0
T20	325452	15	0	0
T21	0	17	0	0
T22	0	39	0	0
T32	942	0	0	0
T33	1442	0	0	0
T34	1456	0	0	0
T35	1637	0	0	0
T42	2930	0	0	0
T48	0	17	0	0
T49	0	114	0	0
T50	0	82	0	0
T95	8496	0	0	0
T132	0	20	0	0
T133	0	35	0	0
T134	0	10	0	0
T135	0	14	0	0
T136	2094	0	0	0
T137	53284	0	0	0
T138	23160	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27211304	42562	0	0
T9	7660	40	0	0
T10	1691	0	0	0
T11	15618	0	0	0
T12	15089	0	0	0
T13	62831	0	0	0
T20	0	801	0	0
T23	17936	151	0	0
T24	2599	0	0	0
T25	6558	0	0	0
T29	0	9	0	0
T30	0	55	0	0
T33	0	11	0	0
T53	7188	49	0	0
T57	0	34	0	0
T80	2063	0	0	0
T81	0	29	0	0
T99	0	77	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27211304	1453	0	0
T20	325452	2	0	0
T32	942	0	0	0
T33	1442	0	0	0
T34	1456	0	0	0
T35	1637	0	0	0
T42	2930	0	0	0
T48	0	4	0	0
T74	0	1	0	0
T83	0	12	0	0
T95	8496	0	0	0
T135	0	12	0	0
T136	2094	0	0	0
T137	53284	0	0	0
T138	23160	0	0	0
T139	0	4	0	0
T140	0	7	0	0
T141	0	12	0	0
T142	0	9	0	0
T143	0	14	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27211304	1252	0	0
T20	325452	7	0	0
T32	942	0	0	0
T33	1442	0	0	0
T34	1456	0	0	0
T35	1637	0	0	0
T42	2930	0	0	0
T74	0	10	0	0
T83	0	10	0	0
T95	8496	0	0	0
T135	0	5	0	0
T136	2094	0	0	0
T137	53284	0	0	0
T138	23160	0	0	0
T139	0	9	0	0
T140	0	6	0	0
T141	0	4	0	0
T142	0	3	0	0
T143	0	15	0	0
T144	0	16	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27211304	1373	0	0
T48	393519	15	0	0
T49	483194	0	0	0
T74	0	12	0	0
T83	0	11	0	0
T85	1340	0	0	0
T86	1523	0	0	0
T87	2912	0	0	0
T88	42659	0	0	0
T89	5607	0	0	0
T90	1621	0	0	0
T91	21734	0	0	0
T92	13108	0	0	0
T135	0	17	0	0
T139	0	2	0	0
T140	0	9	0	0
T141	0	5	0	0
T142	0	4	0	0
T143	0	19	0	0
T144	0	18	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27211304	2080	0	0
T74	0	11	0	0
T83	0	14	0	0
T135	587553	15	0	0
T139	0	10	0	0
T140	0	9	0	0
T141	0	14	0	0
T142	0	10	0	0
T143	0	15	0	0
T144	0	8	0	0
T145	0	4	0	0
T146	59502	0	0	0
T147	19706	0	0	0
T148	138022	0	0	0
T149	3513	0	0	0
T150	2167	0	0	0
T151	2136	0	0	0
T152	28812	0	0	0
T153	1826	0	0	0
T154	15312	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27211304	1399	0	0
T20	325452	2	0	0
T32	942	0	0	0
T33	1442	0	0	0
T34	1456	0	0	0
T35	1637	0	0	0
T42	2930	0	0	0
T48	0	1	0	0
T74	0	20	0	0
T83	0	7	0	0
T95	8496	0	0	0
T135	0	4	0	0
T136	2094	0	0	0
T137	53284	0	0	0
T138	23160	0	0	0
T139	0	2	0	0
T140	0	10	0	0
T141	0	3	0	0
T142	0	8	0	0
T143	0	17	0	0