Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	79784034	155934	0	0
StatusRise_A	79784034	173757	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79784034	155934	0	0
T1	9714	12	0	0
T2	177102	493	0	0
T3	11982	0	0	0
T4	8769	40	0	0
T5	6462	12	0	0
T6	16965	21	0	0
T7	7794	12	0	0
T8	2415	3	0	0
T9	22980	64	0	0
T10	5073	12	0	0
T13	0	527	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79784034	173757	0	0
T1	9714	15	0	0
T2	177102	549	0	0
T3	11982	18	0	0
T4	8769	43	0	0
T5	6462	15	0	0
T6	16965	27	0	0
T7	7794	15	0	0
T8	2415	9	0	0
T9	22980	69	0	0
T10	5073	15	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	26594678	57767	0	0
StatusRise_A	26594678	64205	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26594678	57767	0	0
T1	3238	4	0	0
T2	59034	182	0	0
T3	3994	0	0	0
T4	2923	15	0	0
T5	2154	4	0	0
T6	5655	7	0	0
T7	2598	4	0	0
T8	805	1	0	0
T9	7660	25	0	0
T10	1691	4	0	0
T13	0	201	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26594678	64205	0	0
T1	3238	5	0	0
T2	59034	202	0	0
T3	3994	6	0	0
T4	2923	16	0	0
T5	2154	5	0	0
T6	5655	9	0	0
T7	2598	5	0	0
T8	805	3	0	0
T9	7660	27	0	0
T10	1691	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	26594678	57769	0	0
StatusRise_A	26594678	64205	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26594678	57769	0	0
T1	3238	4	0	0
T2	59034	182	0	0
T3	3994	0	0	0
T4	2923	15	0	0
T5	2154	4	0	0
T6	5655	7	0	0
T7	2598	4	0	0
T8	805	1	0	0
T9	7660	25	0	0
T10	1691	4	0	0
T13	0	201	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26594678	64205	0	0
T1	3238	5	0	0
T2	59034	202	0	0
T3	3994	6	0	0
T4	2923	16	0	0
T5	2154	5	0	0
T6	5655	9	0	0
T7	2598	5	0	0
T8	805	3	0	0
T9	7660	27	0	0
T10	1691	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	26594678	40398	0	0
StatusRise_A	26594678	45347	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26594678	40398	0	0
T1	3238	4	0	0
T2	59034	129	0	0
T3	3994	0	0	0
T4	2923	10	0	0
T5	2154	4	0	0
T6	5655	7	0	0
T7	2598	4	0	0
T8	805	1	0	0
T9	7660	14	0	0
T10	1691	4	0	0
T13	0	125	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26594678	45347	0	0
T1	3238	5	0	0
T2	59034	145	0	0
T3	3994	6	0	0
T4	2923	11	0	0
T5	2154	5	0	0
T6	5655	9	0	0
T7	2598	5	0	0
T8	805	3	0	0
T9	7660	15	0	0
T10	1691	5	0	0